| /Documentation/devicetree/bindings/fpga/ |
| D | altera-hps2fpga-bridge.txt | 1 Altera FPGA/HPS Bridge Driver
4 - regs : base address and size for AXI bridge module
6 "altr,socfpga-lwhps2fpga-bridge",
7 "altr,socfpga-hps2fpga-bridge", or
8 "altr,socfpga-fpga2hps-bridge"
9 - resets : Phandle and reset specifier for this bridge's reset
12 See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
15 fpga_bridge0: fpga-bridge@ff400000 {
16 compatible = "altr,socfpga-lwhps2fpga-bridge";
20 bridge-enable = <0>;
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| D | altera-freeze-bridge.txt | 1 Altera Freeze Bridge Controller Driver
3 The Altera Freeze Bridge Controller manages one or more freeze bridges.
5 changes from passing through the bridge. The controller can also
7 bridge normally.
10 - compatible : Should contain "altr,freeze-bridge-controller"
11 - regs : base address and size for freeze bridge module
13 See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
17 compatible = "altr,freeze-bridge-controller";
19 bridge-enable = <0>;
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| D | fpga-bridge.txt | 1 FPGA Bridge Device Tree Binding
4 - bridge-enable : 0 if driver should disable bridge at startup
5 1 if driver should enable bridge at startup
6 Default is to leave bridge in current state.
9 fpga_bridge3: fpga-bridge@ffc25080 {
10 compatible = "altr,socfpga-fpga2sdram-bridge";
12 bridge-enable = <0>;
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| D | altera-fpga2sdram-bridge.txt | 1 Altera FPGA To SDRAM Bridge Driver
4 - compatible : Should contain "altr,socfpga-fpga2sdram-bridge"
6 See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
9 fpga_bridge3: fpga-bridge@ffc25080 {
10 compatible = "altr,socfpga-fpga2sdram-bridge";
12 bridge-enable = <0>;
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| D | xilinx-pr-decoupler.txt | 6 changes from passing through the bridge. The controller can also
8 bridge normally.
22 Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
25 fpga-bridge@100000450 {
31 bridge-enable = <0>;
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| /Documentation/driver-api/fpga/ |
| D | fpga-bridge.rst | 1 FPGA Bridge
4 API to implement a new FPGA bridge
7 * struct fpga_bridge — The FPGA Bridge structure
8 * struct fpga_bridge_ops — Low level Bridge driver ops
9 * devm_fpga_bridge_create() — Allocate and init a bridge struct
10 * fpga_bridge_register() — Register a bridge
11 * fpga_bridge_unregister() — Unregister a bridge
13 .. kernel-doc:: include/linux/fpga/fpga-bridge.h
16 .. kernel-doc:: include/linux/fpga/fpga-bridge.h
19 .. kernel-doc:: drivers/fpga/fpga-bridge.c
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| /Documentation/networking/device_drivers/ethernet/ti/ |
| D | cpsw_switchdev.rst | 34 to the same bridge, but without enabling "switch" mode, or to different
63 which, by default, equal CPSW Port numbers. As result, bridge has to be
66 ip link add name br0 type bridge
67 ip link set dev br0 type bridge vlan_filtering 0
68 echo 0 > /sys/class/net/br0/bridge/default_pvid
74 ip link add name br0 type bridge
75 ip link set dev br0 type bridge vlan_filtering 0
76 echo 100 > /sys/class/net/br0/bridge/default_pvid
77 ip link set dev br0 type bridge vlan_filtering 1
91 Port's netdev devices have to be in UP before joining to the bridge to avoid
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| /Documentation/networking/dsa/ |
| D | configuration.rst | 21 *bridge*
22 Every switch port is part of one configurable Ethernet bridge
26 Ethernet bridge.
65 *bridge*
99 bridge section in Configuration with tagging support
112 # create bridge
113 ip link add name br0 type bridge
115 # add ports to bridge
120 # configure the bridge
123 # bring up the bridge
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| D | b53.rst | 57 VLAN configuration in the bridge showcase.
61 The configuration can only be set up via VLAN tagging and bridge setup.
82 # create bridge
83 ip link add name br0 type bridge
86 ip link set dev br0 type bridge vlan_filtering 1
94 bridge vlan add dev lan1 vid 2 pvid untagged
95 bridge vlan del dev lan1 vid 1
96 bridge vlan add dev lan2 vid 3 pvid untagged
97 bridge vlan del dev lan2 vid 1
104 # bring up the bridge devices
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| D | dsa.rst | 18 Linux tools such as bridge, iproute2, ifconfig to work transparently whether
322 DSA directly utilizes SWITCHDEV when interfacing with the bridge layer, and
467 ``BR_STATE_BLOCKING`` if the port is a bridge member, or ``BR_STATE_FORWARDING`` if it
474 disabled while being a bridge member
476 Bridge layer
479 - ``port_bridge_join``: bridge layer function invoked when a given switch port is
480 added to a bridge, this function should be doing the necessary at the switch
482 domain for it to ingress/egress traffic with other members of the bridge.
484 - ``port_bridge_leave``: bridge layer function invoked when a given switch port is
485 removed from a bridge, this function should be doing the necessary at the
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | marvell,orion-intc.txt | 26 * Bridge interrupt controller
29 - compatible: shall be "marvell,orion-bridge-intc"
30 - reg: base address of bridge interrupt registers starting with CAUSE register
31 - interrupts: bridge interrupt of the main interrupt controller
36 - marvell,#interrupts: number of interrupts provided by bridge interrupt
41 compatible = "marvell,orion-bridge-intc";
46 /* Dove bridge provides 5 interrupts */
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| /Documentation/devicetree/bindings/ata/ |
| D | cortina,gemini-sata-bridge.txt | 1 * Cortina Systems Gemini SATA Bridge
3 The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
9 "cortina,gemini-sata-bridge"
37 - cortina,gemini-enable-sata-bridge: enables the PATA to SATA bridge
44 compatible = "cortina,gemini-sata-bridge";
54 cortina,gemini-enable-sata-bridge;
|
| /Documentation/networking/ |
| D | bridge.rst | 11 http://www.linuxfoundation.org/collaborate/workgroups/networking/bridge
13 The bridge-utilities are maintained at:
14 git://git.kernel.org/pub/scm/linux/kernel/git/shemminger/bridge-utils.git
17 bridge devices.
20 (more info https://lists.linux-foundation.org/mailman/listinfo/bridge).
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| D | switchdev.rst | 154 together to form a LAG. Two or more ports (or LAGs) can be bridged to bridge
157 tools such as the bridge driver, the bonding/team drivers, and netlink-based
162 bond will see it's upper master change. If that bond is moved into a bridge,
171 to the switchdev device by mirroring bridge FDB entries down to the device. An
176 - Static FDB entries installed on a bridge port
185 to support static FDB entries installed to the device. Static bridge FDB
186 entries are installed, for example, using iproute2 bridge cmd::
188 bridge fdb add ADDR dev DEV [vlan VID] [self]
197 Note: by default, the bridge does not filter on VLAN and only bridges untagged
200 echo 1 >/sys/class/net/<bridge>/bridge/vlan_filtering
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | simple-bridge.yaml | 4 $id: http://devicetree.org/schemas/display/bridge/simple-bridge.yaml#
46 description: The bridge input
50 description: The bridge output
60 description: GPIO controlling bridge enable
64 description: Power supply for the bridge
74 bridge {
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| D | cdns,mhdp8546.yaml | 4 $id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#"
7 title: Cadence MHDP8546 bridge
40 DP bridge clock, used by the IP to know how to translate a number of
74 First input port representing the DP bridge input.
79 Second input port representing the DP bridge input.
84 Third input port representing the DP bridge input.
89 Fourth input port representing the DP bridge input.
94 Output port representing the DP bridge output.
140 mhdp: dp-bridge@f0fb000000 {
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| /Documentation/PCI/ |
| D | acpi-info.rst | 11 host bridges, so the ACPI namespace must describe each host bridge, the
13 the host bridge forwards to PCI (using _CRS), and the routing of legacy
16 PCI devices, which are below the host bridge, generally do not need to be
46 they forward down to the PCI bus, as well as registers of the host bridge
47 itself that are not forwarded to PCI. The host bridge registers include
49 range below the bridge, window registers that describe the apertures, etc.
52 the device-specific details. The host bridge registers also include ECAM
53 space, since it is consumed by the host bridge.
55 ACPI defines a Consumer/Producer bit to distinguish the bridge registers
56 ("Consumer") from the bridge apertures ("Producer") [4, 5], but early
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| /Documentation/ABI/testing/ |
| D | sysfs-class-fpga-bridge | 1 What: /sys/class/fpga_bridge/<bridge>/name
5 Description: Name of low level FPGA bridge driver.
7 What: /sys/class/fpga_bridge/<bridge>/state
11 Description: Show bridge state as "enabled" or "disabled"
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| /Documentation/devicetree/bindings/pci/ |
| D | pci.txt | 11 Additionally to the properties specified in the above standards a host bridge
15 If present this property assigns a fixed PCI domain number to a host bridge,
20 number for each host bridge in the system must be unique.
32 root port to downstream device and host bridge drivers can do programming
36 PCI-PCI Bridge properties
40 tree, as children of the host bridge node. Even though those devices are
47 Identifies the PCI-PCI bridge. As defined in the IEEE Std 1275-1994
52 The bus number is defined by firmware, through the standard bridge
55 register of the bridge directly above this port. Otherwise, the bus
59 If firmware leaves the ARI Forwarding Enable bit set in the bridge
|
| /Documentation/s390/ |
| D | qeth.rst | 5 OSA and HiperSockets Bridge Port Support
12 a primary or a secondary Bridge Port. For more information, see
15 When run on an OSA or HiperSockets Bridge Capable Port hardware, and the state
16 of some configured Bridge Port device on the channel changes, a udev
21 indicates that the Bridge Port device changed
30 When run on HiperSockets Bridge Capable Port hardware with host address
39 deregistered on the Bridge Port HiperSockets channel, or address
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| /Documentation/devicetree/bindings/clock/ |
| D | armada3700-periph-clock.txt | 6 There are two different blocks associated to north bridge and south
7 bridge.
12 The following is a list of provided IDs for Armada 3700 North bridge clocks:
33 The following is a list of provided IDs for Armada 3700 South bridge clocks:
54 north bridge block, or
55 "marvell,armada-3700-periph-clock-sb" for the south bridge block
56 - reg : must be the register address of North/South Bridge Clock register
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| /Documentation/devicetree/bindings/sound/ |
| D | st,sta350.txt | 23 0: 2-channel (full-bridge) power, 2-channel data-out
24 1: 2 (half-bridge). 1 (full-bridge) on-board power
25 2: 2 Channel (Full-Bridge) Power, 1 Channel FFX
71 If present, power bridge correction for THD reduction near maximum
93 - st,bridge-immediate-off:
94 If present, the bridge will be switched off immediately after the
95 power-down-gpio goes low. Otherwise, the bridge will wait for 13
108 If present, the bridge power-down time will be divided by the provided
121 // (full-bridge) power,
126 st,max-power-correction; // enables power bridge
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| /Documentation/devicetree/bindings/mmc/ |
| D | socionext,uniphier-sd.yaml | 33 bridge: exist only for version 2.91
39 - const: bridge
45 - const: bridge
64 const: bridge
70 const: bridge
92 reset-names = "host", "bridge";
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| /Documentation/devicetree/bindings/soc/mediatek/ |
| D | pwrap.txt | 15 bridge. In the binding description below the properties needed for bridging
33 "pwrap-bridge": bridge base (IP Pairing)
37 "pwrap-bridge" (IP Pairing)
57 reg-names = "pwrap", "pwrap-bridge";
61 reset-names = "pwrap", "pwrap-bridge";
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| /Documentation/i2c/busses/ |
| D | i2c-sis630.rst | 40 00:00.0 Host bridge: Silicon Integrated Systems [SiS] 630 Host (rev 31)
41 00:01.0 ISA bridge: Silicon Integrated Systems [SiS] 85C503/5513
45 00:00.0 Host bridge: Silicon Integrated Systems [SiS] 730 Host (rev 02)
46 00:01.0 ISA bridge: Silicon Integrated Systems [SiS] 85C503/5513
50 00:00.0 Host bridge: Silicon Integrated Systems [SiS] 760/M760 Host (rev 02)
51 00:02.0 ISA bridge: Silicon Integrated Systems [SiS] SiS964 [MuTIOL Media IO]
|