Searched full:chips (Results 1 – 25 of 412) sorted by relevance
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| /Documentation/devicetree/bindings/bus/ |
| D | brcm,gisb-arb.txt | 6 "brcm,bcm7278-gisb-arb" for V7 28nm chips
7 "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for other 28nm chips
8 "brcm,bcm7435-gisb-arb" for newer 40nm chips
9 "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips
10 "brcm,bcm7038-gisb-arb" for 130nm chips
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| /Documentation/hwmon/ |
| D | tmp421.rst | 4 Supported chips:
54 TMP423, TMP441, and TMP442 temperature sensor chips. These chips
57 in degrees Celsius. The chips are wired over I2C/SMBus and specified
61 The chips support only temperature measurement. The driver exports
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| D | thmc50.rst | 4 Supported chips:
38 List of adapter,address pairs to force chips into ADM1022 mode with
39 second remote temperature. This does not work for original THMC50 chips.
57 The THMC50 is usually used in combination with LM78-like chips, to measure
88 The driver was tested on Compaq AP550 with two ADM1022 chips (one works
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| D | it87.rst | 4 Supported chips:
175 Force PWM polarity to active high (DANGEROUS). Some chips are
183 All the chips supported by this driver are LPC Super-I/O chips, accessed
197 SiS950 chips.
199 These chips are 'Super I/O chips', supporting floppy disks, infrared ports,
224 not compatible with the older chips and revisions. The 16-bit tachometer mode
225 is enabled by the driver when one of the above chips is detected.
239 to IT8728F. It only supports 16-bit fan mode. Both chips support up to 6 fans.
260 zero'; this is important for negative voltage measurements. On most chips, all
304 "Smart Guardian" mode control handling is only implemented for older chips
[all …]
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| D | tmp401.rst | 4 Supported chips:
63 TMP431, TMP432, TMP435, and TMP461 chips. These chips implement one or two
73 The TMP411 and TMP431 chips are compatible with TMP401. TMP411 provides
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| D | emc1403.rst | 4 Supported chips:
55 The Standard Microsystems Corporation (SMSC) / Microchip EMC14xx chips
61 The chips implement three limits for each sensor: low (tempX_min), high
62 (tempX_max) and critical (tempX_crit.) The chips also implement an
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| D | adm1021.rst | 4 Supported chips:
101 The chips supported by this driver are very similar. The Maxim MAX1617 is
104 Ditto for the THMC10. From here on, we will refer to all these chips as
135 2003) microarchitecture had real MAX1617, ADM1021, or compatible chips
137 era (with 400 MHz FSB) had chips with only one temperature sensor.
144 will have to explicitly instantiate the sensor chips from user-space. See
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| D | userspace-tools.rst | 7 Most mainboards have sensor chips to monitor system health (like temperatures,
11 The kernel drivers make the data from the sensor chips available in the /sys
13 values or configure the chips in a more friendly manner.
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| D | smsc47m1.rst | 4 Supported chips:
56 The Standard Microsystems Corporation (SMSC) 47M1xx Super I/O chips
59 The LPC47M15x, LPC47M192 and LPC47M292 chips contain a full 'hardware
65 ID as the 47M15x and 47M192 chips and seems to be compatible.
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| D | lm75.rst | 4 Supported chips:
149 slowest chips and 125 ms for the fastest chips; reading it more often
152 The original LM75 was typically used in combination with LM78-like chips
164 Both chips are simply not compatible, value encoding differs.
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| D | sch5627.rst | 4 Supported chips:
20 SMSC SCH5627 Super I/O chips include complete hardware monitoring
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| D | w83627hf.rst | 4 Supported chips:
42 the Winbond W83627HF, W83627THF, W83697HF and W83637HF Super I/O chips.
43 We will refer to them collectively as Winbond chips.
51 If you really want i2c accesses for these Super I/O chips,
57 VID reading. However the two chips have the identical 128 pin package. So,
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| D | jc42.rst | 4 Supported chips:
88 * JEDEC JC 42.4 compliant temperature sensor chips
95 Common for all chips:
113 The driver auto-detects the chips listed above, but can be manually instantiated
114 to support other JC 42.4 compliant chips.
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | ccf.txt | 12 Example chips: T4240, B4860
15 Example chips: P5040, P5020, P4080, P3041, P2041
20 used for both CCF version 1 chips and CCF version 2
21 chips. It should be specified after either
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| /Documentation/admin-guide/gpio/ |
| D | gpio-mockup.rst | 7 chips for testing purposes. The lines exposed by these chips can be accessed
11 Creating simulated chips using module params
26 The line above creates three chips. The first one will expose 8 lines,
28 to 405 while for two first chips it will be assigned automatically.
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| /Documentation/devicetree/bindings/mtd/ |
| D | jedec,spi-nor.txt | 1 * SPI NOR flash: ST M25Pxx (and similar) serial flash chips
51 designate quirky versions of flash chips that do not support the
69 all chips and support for it can not be detected at runtime.
70 Refer to your chips' datasheet to check if this is supported
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| D | cypress,hyperflash.txt | 1 Bindings for HyperFlash NOR flash chips compliant with Cypress HyperBus
5 - compatible : "cypress,hyperflash", "cfi-flash" for HyperFlash NOR chips
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| D | arm-versatile.txt | 3 These flash chips are found in the ARM reference designs like Integrator,
6 They are regular CFI compatible (Intel or AMD extended) flash chips with
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-max3191x.txt | 17 Number of chips in the daisy-chain (default is 1).
21 (if all chips are wired to the same pin).
30 - maxim,modesel-8bit: Boolean whether the modesel pin of the chips is
39 (in 16-bit mode). Use this if the chips are powered
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| /Documentation/devicetree/bindings/net/ |
| D | marvell-bluetooth.txt | 1 Marvell Bluetooth Chips
5 attached Marvell Bluetooth devices. The following chips are included in
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| /Documentation/i2c/ |
| D | summary.rst | 23 and hardware monitoring chips.
35 one or more *master* chips and one or more *slave* chips.
55 video-related chips.
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| /Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra20-ahb.txt | 9 Tegra20, Tegra30, and Tegra114 chips, the value must be <0x6000c004
10 0x10c>. For Tegra124, Tegra132 and Tegra210 chips, the value should
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| /Documentation/i2c/busses/ |
| D | i2c-i801.rst | 81 ICH3 (82801CA/CAM) and later devices (PCH) are Intel chips that are a part of
85 The ICH chips contain at least SEVEN separate PCI functions in TWO logical
98 The ICH chips are quite similar to Intel's PIIX4 chip, at least in the
105 Block process call is supported on the 82801EB (ICH5) and later chips.
111 I2C block read is supported on the 82801EB (ICH5) and later chips.
117 The 82801DB (ICH4) and later chips support several SMBus 2.0 features.
123 PCI interrupt support is supported on the 82801EB (ICH5) and later chips.
169 If it works, proves useful (i.e. there are usable chips on the SMBus)
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| /Documentation/devicetree/bindings/media/ |
| D | si4713.txt | 13 - interrupts-extended: Interrupt specifier for the chips interrupt
14 - reset-gpios: GPIO specifier for the chips reset line
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | pinctrl-mcp23s08.txt | 28 multiple chips on the same chipselect. Have a look at
31 Required device specific properties (only for SPI chips):
34 chips - as the name suggests. Multiple SPI chips can share the same
40 least one bit to 1 for SPI chips.
57 IO 8-15 are bank 2. These chips have two different interrupt outputs:
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