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/Documentation/devicetree/bindings/sound/
Dnvidia,tegra20-ac97.txt4 - compatible : "nvidia,tegra20-ac97"
5 - reg : Should contain AC97 controller registers location and length
6 - interrupts : Should contain AC97 interrupt
7 - resets : Must contain an entry for each entry in reset-names.
8 See ../reset/reset.txt for details.
9 - reset-names : Must include the following entries:
10 - ac97
11 - dmas : Must contain an entry for each entry in clock-names.
13 - dma-names : Must include the following entries:
14 - rx
[all …]
Dtlv320aic3x.txt1 Texas Instruments - tlv320aic3x Codec module
7 - compatible - "string" - One of:
8 "ti,tlv320aic3x" - Generic TLV320AIC3x device
9 "ti,tlv320aic33" - TLV320AIC33
10 "ti,tlv320aic3007" - TLV320AIC3007
11 "ti,tlv320aic3106" - TLV320AIC3106
12 "ti,tlv320aic3104" - TLV320AIC3104
15 - reg - <int> - I2C slave address
20 - reset-gpios - GPIO specification for the active low RESET input.
21 - ai3x-gpio-func - <array of 2 int> - AIC3X_GPIO1 & AIC3X_GPIO2 Functionality
[all …]
Dcs4270.txt1 CS4270 audio CODEC
7 - compatible : "cirrus,cs4270"
9 - reg : the I2C address of the device for I2C
13 - reset-gpios : a GPIO spec for the reset pin. If specified, it will be
14 deasserted before communication to the codec starts.
18 codec: cs4270@48 {
Dcs4349.txt1 CS4349 audio CODEC
5 - compatible : "cirrus,cs4349"
7 - reg : the I2C address of the device for I2C
11 - reset-gpios : a GPIO spec for the reset pin.
15 codec: cs4349@48 {
18 reset-gpios = <&gpio 54 0>;
Dcs42l52.txt1 CS42L52 audio CODEC
5 - compatible : "cirrus,cs42l52"
7 - reg : the I2C address of the device for I2C
11 - cirrus,reset-gpio : GPIO controller's phandle and the number
12 of the GPIO used to reset the codec.
14 - cirrus,chgfreq-divisor : Values used to set the Charge Pump Frequency.
21 - cirrus,mica-differential-cfg : boolean, If present, then the MICA input is configured
23 Single-ended input. Single-ended mode allows for MIC1 or MIC2 muxing for input.
25 - cirrus,micb-differential-cfg : boolean, If present, then the MICB input is configured
27 Single-ended input. Single-ended mode allows for MIC1 or MIC2 muxing for input.
[all …]
Dpcm1789.txt3 PCM1789 is a simple audio codec that can be connected via
8 - compatible: "ti,pcm1789"
12 - reg: the I2C address
13 - reset-gpios: GPIO to control the RESET pin
17 audio-codec@4c {
20 reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
21 #sound-dai-cells = <0>;
Dtlv320aic31xx.txt1 Texas Instruments - tlv320aic31xx Codec module
7 - compatible - "string" - One of:
8 "ti,tlv320aic310x" - Generic TLV320AIC31xx with mono speaker amp
9 "ti,tlv320aic311x" - Generic TLV320AIC31xx with stereo speaker amp
10 "ti,tlv320aic3100" - TLV320AIC3100 (mono speaker amp, no MiniDSP)
11 "ti,tlv320aic3110" - TLV320AIC3110 (stereo speaker amp, no MiniDSP)
12 "ti,tlv320aic3120" - TLV320AIC3120 (mono speaker amp, MiniDSP)
13 "ti,tlv320aic3111" - TLV320AIC3111 (stereo speaker amp, MiniDSP)
14 "ti,tlv320dac3100" - TLV320DAC3100 (no ADC, mono speaker amp, no MiniDSP)
15 "ti,tlv320dac3101" - TLV320DAC3101 (no ADC, stereo speaker amp, no MiniDSP)
[all …]
Drt5677.txt1 RT5677 audio CODEC
7 - compatible : "realtek,rt5677".
9 - reg : The I2C address of the device.
11 - interrupts : The CODEC's interrupt output.
13 - gpio-controller : Indicates this device is a GPIO controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and the
20 - realtek,pow-ldo2-gpio : The GPIO that controls the CODEC's POW_LDO2 pin.
21 - realtek,reset-gpio : The GPIO that controls the CODEC's RESET pin. Active low.
23 - realtek,in1-differential
24 - realtek,in2-differential
[all …]
Drt5659.txt1 RT5659/RT5658 audio CODEC
7 - compatible : One of "realtek,rt5659" or "realtek,rt5658".
9 - reg : The I2C address of the device.
11 - interrupts : The CODEC's interrupt output.
15 - clocks: The phandle of the master clock to the CODEC
16 - clock-names: Should be "mclk"
18 - realtek,in1-differential
19 - realtek,in3-differential
20 - realtek,in4-differential
21 Boolean. Indicate MIC1/3/4 input are differential, rather than single-ended.
[all …]
Dti,pcm3168a.txt3 This driver supports both SPI and I2C bus access for this codec
7 - compatible: "ti,pcm3168a"
9 - clocks : Contains an entry for each entry in clock-names
11 - clock-names : Includes the following entries:
14 - VDD1-supply : Digital power supply regulator 1 (+3.3V)
16 - VDD2-supply : Digital power supply regulator 2 (+3.3V)
18 - VCCAD1-supply : ADC power supply regulator 1 (+5V)
20 - VCCAD2-supply : ADC power supply regulator 2 (+5V)
22 - VCCDA1-supply : DAC power supply regulator 1 (+5V)
24 - VCCDA2-supply : DAC power supply regulator 2 (+5V)
[all …]
Dcs35l32.txt1 CS35L32 audio CODEC
5 - compatible : "cirrus,cs35l32"
7 - reg : the I2C address of the device for I2C. Address is determined by the level
10 - VA-supply, VP-supply : power supplies for the device,
15 - reset-gpios : a GPIO spec for the reset pin. If specified, it will be
16 deasserted before communication to the codec starts.
18 - cirrus,boost-manager : Boost voltage control.
19 0 = Automatically managed. Boost-converter output voltage is the higher
21 1 = Automatically managed irrespective of audio, adapting for low-power
22 dissipation when LEDs are ON, and operating in Fixed-Boost Bypass Mode
[all …]
Dcs4271.txt7 - compatible: "cirrus,cs4271"
10 Documentation/devicetree/bindings/spi/spi-bus.txt
14 - reg: the i2c address
19 - reset-gpio: a GPIO spec to define which pin is connected to the chip's
20 !RESET pin
21 - cirrus,amuteb-eq-bmutec: When given, the Codec's AMUTEB=BMUTEC flag
23 - cirrus,enable-soft-reset:
24 The CS4271 requires its LRCLK and MCLK to be stable before its RESET
25 line is de-asserted. That also means that clocks cannot be changed
26 without putting the chip back into hardware reset, which also requires
[all …]
Dwm8804.txt1 WM8804 audio CODEC
8 - compatible : "wlf,wm8804"
10 - reg : the I2C address of the device for I2C, the chip select
13 - PVDD-supply, DVDD-supply : Power supplies for the device, as covered
18 - wlf,reset-gpio: A GPIO specifier for the GPIO controlling the reset pin
22 wm8804: codec@1a {
Dcs42xx8.txt1 CS42448/CS42888 audio CODEC
5 - compatible : must contain one of "cirrus,cs42448" and "cirrus,cs42888"
7 - reg : the I2C address of the device for I2C
9 - clocks : a list of phandles + clock-specifiers, one for each entry in
10 clock-names
12 - clock-names : must contain "mclk"
14 - VA-supply, VD-supply, VLS-supply, VLC-supply: power supplies for the device,
19 - reset-gpios : a GPIO spec to define which pin is connected to the chip's
20 !RESET pin
24 cs42888: codec@48 {
[all …]
Dtlv320aic32x4.txt1 Texas Instruments - tlv320aic32x4 Codec module
6 - compatible - "string" - One of:
9 - reg: I2C slave address
10 - supply-*: Required supply regulators are:
11 "iov" - digital IO power supply
12 "ldoin" - LDO power supply
13 "dv" - Digital core power supply
14 "av" - Analog core power supply
20 - reset-gpios: Reset-GPIO phandle with args as described in gpio/gpio.txt
21 - clocks/clock-names: Clock named 'mclk' for the master clock of the codec.
[all …]
Dcs4265.txt1 CS4265 audio CODEC
7 - compatible : "cirrus,cs4265"
9 - reg : the I2C address of the device for I2C. The I2C address depends on
15 - reset-gpios : a GPIO spec for the reset pin. If specified, it will be
16 deasserted before communication to the codec starts.
Dtas2764.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Dan Murphy <dmurphy@ti.com>
14 The TAS2764 is a mono, digital input Class-D audio amplifier optimized for
22 - ti,tas2764
29 reset-gpios:
31 description: GPIO used to reset the device.
33 shutdown-gpios:
40 ti,imon-slot-no:
[all …]
Dsocionext,uniphier-evea.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/sound/socionext,uniphier-evea.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier EVEA SoC-internal sound codec
10 - <alsa-devel@alsa-project.org>
14 const: socionext,uniphier-evea
19 clock-names:
21 - const: evea
22 - const: exiv
[all …]
Dcs53l30.txt1 CS53L30 audio CODEC
5 - compatible : "cirrus,cs53l30"
7 - reg : the I2C address of the device
9 - VA-supply, VP-supply : power supplies for the device,
14 - reset-gpios : a GPIO spec for the reset pin.
16 - mute-gpios : a GPIO spec for the MUTE pin. The active state can be either
20 - cirrus,micbias-lvl : Set the output voltage level on the MICBIAS Pin.
21 0 = Hi-Z
25 - cirrus,use-sdout2 : This is a boolean property. If present, it indicates
29 * CS53l30 supports 4-channel data output in the same
[all …]
Dtas2770.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019-20 Texas Instruments Incorporated
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Shi Fu <shifu0704@thundersoft.com>
14 The TAS2770 is a mono, digital input Class-D audio amplifier optimized for
22 - ti,tas2770
29 reset-gpio:
30 description: GPIO used to reset the device.
32 shutdown-gpios:
[all …]
Drohm,bd28623.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 This codec does not have any control buses such as I2C, it detect
12 that can be connected to GPIOs reset and mute.
15 - Katsuhiro Suzuki <katsuhiro@katsuster.net>
21 "#sound-dai-cells":
24 VCCA-supply:
28 VCCP1-supply:
32 VCCP2-supply:
[all …]
Dst,sta32x.txt1 STA32X audio CODEC
7 - compatible: "st,sta32x"
8 - reg: the I2C address of the device for I2C
9 - reset-gpios: a GPIO spec for the reset pin. If specified, it will be
10 deasserted before communication to the codec starts.
12 - power-down-gpios: a GPIO spec for the power down pin. If specified,
13 it will be deasserted before communication to the codec
16 - Vdda-supply: regulator spec, providing 3.3V
17 - Vdd3-supply: regulator spec, providing 3.3V
18 - Vcc-supply: regulator spec, providing 5V - 26V
[all …]
Dqcom,wcd9335.txt1 QCOM WCD9335 Codec
3 Qualcomm WCD9335 Codec is a standalone Hi-Fi audio codec IC, supports
5 the MSM8996, MSM8976, and MSM8956 chipsets. It has in-built
11 - compatible:
21 - reg
26 - interrupts
28 Value type: <prop-encoded-array>
31 - interrupt-names:
37 - reset-gpios:
40 Definition: Reset gpio line
[all …]
/Documentation/devicetree/bindings/mfd/
Dallwinner,sun8i-a23-prcm.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/mfd/allwinner,sun8i-a23-prcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
17 const: allwinner,sun8i-a23-prcm
23 "^.*(clk|rst|codec).*$":
29 - fixed-factor-clock
30 - allwinner,sun8i-a23-apb0-clk
[all …]
/Documentation/devicetree/bindings/pinctrl/
Dcirrus,lochnagar.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
14 Smart CODEC and Amp devices. It allows the connection of most Cirrus
15 Logic devices on mini-cards, as well as allowing connection of various
26 [2] Pinctrl: ../pinctrl/pinctrl-bindings.txt
29 [3] include/dt-bindings/pinctrl/lochnagar.h
37 - cirrus,lochnagar-pinctrl
39 gpio-controller: true
[all …]

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