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/Documentation/devicetree/bindings/arm/
Dcoresight.txt1 * CoreSight Components:
3 CoreSight components are compliant with the ARM CoreSight architecture
8 sink. Each CoreSight component device should use these properties to describe
17 "arm,coresight-etb10", "arm,primecell";
20 "arm,coresight-tpiu", "arm,primecell";
26 "arm,coresight-tmc", "arm,primecell";
29 "arm,coresight-dynamic-funnel", "arm,primecell";
30 "arm,coresight-funnel", "arm,primecell"; (OBSOLETE. For
35 "arm,coresight-etm3x", "arm,primecell";
38 "arm,coresight-etm4x", "arm,primecell";
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Dcoresight-cti.yaml5 $id: http://devicetree.org/schemas/arm/coresight-cti.yaml#
8 title: ARM Coresight Cross Trigger Interface (CTI) device.
11 The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
12 to one or more CoreSight components and/or a CPU, with CTIs interconnected in
15 not part of the CoreSight graph described in the general CoreSight bindings
16 file coresight.txt.
38 indicate this feature (arm,coresight-cti-v8-arch).
49 between CTI and other CoreSight components.
51 Certain triggers between CoreSight devices and the CTI have specific types
53 constants defined in <dt-bindings/arm/coresight-cti-dt.h>
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Dete.yaml16 allows tracing the CPU execution. It overlaps with the CoreSight ETMv4
18 The trace generated by the ETE could be stored via legacy CoreSight
21 legacy CoreSight components, a node must be listed per instance, along
22 with any optional connection graph as per the coresight bindings.
23 See bindings/arm/coresight.txt.
39 Output connections from the ETE to legacy CoreSight trace bus.
43 description: Output connection from the ETE to legacy CoreSight Trace bus.
54 # An ETE node without legacy CoreSight connections
60 # An ETE node with legacy CoreSight connections
66 out-ports { /* legacy coresight connection */
Dcoresight-cpu-debug.txt1 * CoreSight CPU Debug Component:
3 CoreSight CPU debug component are compliant with the ARMv8 architecture
6 external debug, and it can be accessed from mmio region from Coresight
14 - compatible : should be "arm,coresight-cpu-debug"; supplemented with
44 compatible = "arm,coresight-cpu-debug","arm,primecell";
Darm,realview.yaml29 CoreSight and Intelligent Energy Management (IEM) see ARM DUI 0425F.
/Documentation/ABI/testing/
Dsysfs-bus-coresight-devices-cti1 What: /sys/bus/coresight/devices/<cti-name>/enable
7 What: /sys/bus/coresight/devices/<cti-name>/powered
13 What: /sys/bus/coresight/devices/<cti-name>/ctmid
19 What: /sys/bus/coresight/devices/<cti-name>/nr_trigger_cons
25 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/name
31 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/in_signals
37 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/in_types
44 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/out_signals
50 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/out_types
57 What: /sys/bus/coresight/devices/<cti-name>/regs/inout_sel
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Dsysfs-bus-coresight-devices-etm4x1 What: /sys/bus/coresight/devices/etm<N>/enable_source
8 of coresight components linking the source to the sink is
9 configured and managed automatically by the coresight framework.
11 What: /sys/bus/coresight/devices/etm<N>/cpu
17 What: /sys/bus/coresight/devices/etm<N>/nr_pe_cmp
24 What: /sys/bus/coresight/devices/etm<N>/nr_addr_cmp
31 What: /sys/bus/coresight/devices/etm<N>/nr_cntr
38 What: /sys/bus/coresight/devices/etm<N>/nr_ext_inp
44 What: /sys/bus/coresight/devices/etm<N>/numcidc
51 What: /sys/bus/coresight/devices/etm<N>/numvmidc
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Dsysfs-bus-coresight-devices-etm3x1 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/enable_source
8 of coresight components linking the source to the sink is
9 configured and managed automatically by the coresight framework.
11 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_idx
18 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_acctype
29 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_range
37 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_single
45 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_start
53 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_stop
61 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_idx
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Dsysfs-bus-coresight-devices-tmc1 What: /sys/bus/coresight/devices/<memory_map>.tmc/trigger_cntr
10 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rsz
17 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/sts
24 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rrp
33 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rwp
39 the CoreSight bus into the Trace RAM. The value is read directly
42 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/trg
49 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ctl
56 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffsr
64 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffcr
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Dsysfs-bus-coresight-devices-etb101 What: /sys/bus/coresight/devices/<memory_map>.etb/enable_sink
10 echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink
12 What: /sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr
22 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rdp
29 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/sts
36 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rrp
45 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rwp
51 the CoreSight bus into the Trace RAM. The value is read directly
54 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/trg
61 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ctl
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Dsysfs-bus-coresight-devices-stm1 What: /sys/bus/coresight/devices/<memory_map>.stm/enable_source
8 of coresight components linking the source to the sink is
9 configured and managed automatically by the coresight framework.
11 What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_enable
18 What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_select
26 What: /sys/bus/coresight/devices/<memory_map>.stm/port_enable
34 What: /sys/bus/coresight/devices/<memory_map>.stm/port_select
41 What: /sys/bus/coresight/devices/<memory_map>.stm/status
48 What: /sys/bus/coresight/devices/<memory_map>.stm/traceid
Dsysfs-bus-coresight-devices-funnel1 What: /sys/bus/coresight/devices/<memory_map>.funnel/funnel_ctrl
8 What: /sys/bus/coresight/devices/<memory_map>.funnel/priority
Dsysfs-bus-coresight-devices-trbe1 What: /sys/bus/coresight/devices/trbe<cpu>/align
8 What: /sys/bus/coresight/devices/trbe<cpu>/flag
/Documentation/trace/coresight/
Dcoresight-trbe.rst15 gets plugged in as a coresight sink device because the corresponding trace
18 The TRBE is not compliant to CoreSight architecture specifications, but is
19 driven via the CoreSight driver framework to support the ETE (which is
20 CoreSight compliant) integration.
25 The TRBE devices appear on the existing coresight bus alongside the other
26 coresight devices::
28 >$ ls /sys/bus/coresight/devices
33 >$ ls /sys/bus/coresight/devices/trbe0/
Dcoresight.rst2 Coresight - HW Assisted Tracing on ARM
11 Coresight is an umbrella of technologies allowing for the debugging of ARM
24 flows through the coresight system (via ATB bus) using links that are connecting
25 the emanating source to a sink(s). Sinks serve as endpoints to the coresight
28 host without fear of filling up the onboard coresight memory buffer.
30 At typical coresight system would look like this::
85 a way to aggregate and distribute signals between CoreSight components.
87 The coresight framework provides a central point to represent, configure and
88 manage coresight devices on a platform. This first implementation centers on
133 See Documentation/devicetree/bindings/arm/coresight.txt for details.
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Dcoresight-cpu-debug.rst2 Coresight CPU Debug Module
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
107 power down in the way that the CoreSight / Debug designers anticipated.
120 See Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt for details.
183 coresight-cpu-debug 850000.debug: CPU[0]:
184 coresight-cpu-debug 850000.debug: EDPRSR: 00000001 (Power:On DLK:Unlock)
185 coresight-cpu-debug 850000.debug: EDPCSR: handle_IPI+0x174/0x1d8
186 coresight-cpu-debug 850000.debug: EDCIDSR: 00000000
187 …coresight-cpu-debug 850000.debug: EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMI…
188 coresight-cpu-debug 852000.debug: CPU[1]:
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Dcoresight-ect.rst4 CoreSight Embedded Cross Trigger (CTI & CTM).
13 The CoreSight Cross Trigger Interface (CTI) is a hardware device that takes
41 CoreSight devices on the trace data path. When these devices are enabled the
50 The hardware trigger signals can also be connected to non-CoreSight devices
62 The CTI devices appear on the existing CoreSight bus alongside the other
63 CoreSight devices::
65 >$ ls /sys/bus/coresight/devices
71 can be associated with other CoreSight devices, or other system hardware
74 >$ ls /sys/bus/coresight/devices/etm0/cti_cpu0
91 * ``mgmt``: the standard CoreSight management registers.
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Dindex.rst2 CoreSight - ARM Hardware Trace
Dcoresight-etm4x-reference.rst13 Root: ``/sys/bus/coresight/devices/etm<N>``
/Documentation/trace/
Dindex.rst30 coresight/index
Dstm.rst93 Examples of STM devices are Intel(R) Trace Hub [1] and Coresight STM
/Documentation/devicetree/bindings/clock/
Dexynos5433-clock.txt38 which generates clocks for Cortex-A57 Quad-core processor, CoreSight and