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/Documentation/hwmon/
Dsmm665.rst79 Each monitored channel has its own high and low limits, plus a critical
149 in1_lcrit 12v input critical minimum voltage (mV)
150 in2_lcrit 3.3V (VDD) input critical minimum voltage (mV)
151 in3_lcrit Channel A critical minimum voltage (mV)
152 in4_lcrit Channel B critical minimum voltage (mV)
153 in5_lcrit Channel C critical minimum voltage (mV)
154 in6_lcrit Channel D critical minimum voltage (mV)
155 in7_lcrit Channel E critical minimum voltage (mV)
156 in8_lcrit Channel F critical minimum voltage (mV)
157 in9_lcrit AIN1 critical minimum voltage (mV)
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Disl68137.rst436 curr1_crit Critical maximum current
437 curr1_crit_alarm Current critical high alarm
441 curr[2-3]_crit Critical maximum current
442 curr[2-3]_crit_alarm Current critical high alarm
446 in1_lcrit Critical minimum input voltage
447 in1_lcrit_alarm Input voltage critical low alarm
448 in1_crit Critical maximum input voltage
449 in1_crit_alarm Input voltage critical high alarm
453 in[2-3]_lcrit Critical minimum output voltage
454 in[2-3]_lcrit_alarm Output voltage critical low alarm
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Dir38064.rst35 curr1_crit Critical maximum current
36 curr1_crit_alarm Current critical high alarm
42 in1_crit Critical maximum input voltage
43 in1_crit_alarm Input voltage critical high alarm
49 in2_lcrit Critical minimum output voltage
50 in2_lcrit_alarm Output voltage critical low alarm
51 in2_crit Critical maximum output voltage
52 in2_crit_alarm Output voltage critical high alarm
62 temp1_crit Critical high temperature
63 temp1_crit_alarm Chip temperature critical high alarm
Dzl6100.rst169 in1_lcrit Critical minimum input voltage.
170 in1_crit Critical maximum input voltage.
173 in1_lcrit_alarm Input voltage critical low alarm.
174 in1_crit_alarm Input voltage critical high alarm.
180 in2_lcrit Critical minimum VMON/VDRV Voltage.
181 in2_crit Critical maximum VMON/VDRV voltage.
182 in2_lcrit_alarm VMON/VDRV voltage critical low alarm.
183 in2_crit_alarm VMON/VDRV voltage critical high alarm.
190 inX_lcrit Critical minimum output Voltage.
191 inX_crit Critical maximum output voltage.
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Dtps53679.rst80 in1_lcrit Critical minimum input voltage
84 in1_lcrit_alarm Input voltage critical low alarm.
88 in1_crit Critical maximum input voltage.
90 in1_crit_alarm Input voltage critical high alarm.
99 in[N]_lcrit Critical minimum input voltage.
103 in[N]_lcrit_alarm Critical minimum voltage alarm.
111 in[N]_crit Critical maximum output voltage.
115 in[N]_crit_alarm Output voltage critical high alarm.
126 temp[N]_crit Critical high temperature.
130 temp[N]_crit_alarm Temperature critical high alarm.
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Dpxe1610.rst80 curr[2-4]_crit Critical maximum current
81 curr[2-4]_crit_alarm Current critical high alarm
85 in1_crit Critical maximum input voltage
86 in1_crit_alarm Input voltage critical high alarm
90 in[2-4]_lcrit Critical minimum output voltage
91 in[2-4]_lcrit_alarm Output voltage critical low alarm
92 in[2-4]_crit Critical maximum output voltage
93 in[2-4]_crit_alarm Output voltage critical high alarm
103 temp[1-3]_crit Critical high temperature
104 temp[1-3]_crit_alarm Chip temperature critical high alarm
Dxdpe12284.rst44 The driver provides for current: input, maximum and critical thresholds
45 and maximum and critical alarms. Critical thresholds and critical alarm are
62 The driver provides for voltage: input, critical and low critical thresholds
63 and critical and low critical alarms.
90 The driver provides for temperature: input, maximum and critical thresholds
91 and maximum and critical alarms.
Dir35221.rst46 curr[2-3]_crit Critical maximum current
47 curr[2-3]_crit_alarm Current critical high alarm
55 in1_crit Critical maximum input voltage
56 in1_crit_alarm Input voltage critical high alarm
64 in[2-3]_lcrit Critical minimum output voltage
65 in[2-3]_lcrit_alarm Output voltage critical low alarm
66 in[2-3]_crit Critical maximum output voltage
67 in[2-3]_crit_alarm Output voltage critical high alarm
86 temp[1-2]_crit Critical high temperature
87 temp[1-2]_crit_alarm Chip temperature critical high alarm
Ducd9200.rst65 in1_lcrit Critical minimum Voltage. VIN_UV_FAULT_LIMIT register.
66 in1_crit Critical maximum voltage. From VIN_OV_FAULT_LIMIT
70 in1_lcrit_alarm Voltage critical low alarm. From VIN_UV_FAULT status.
71 in1_crit_alarm Voltage critical high alarm. From VIN_OV_FAULT status.
77 in[2-5]_lcrit Critical minimum Voltage. VOUT_UV_FAULT_LIMIT register.
78 in[2-5]_crit Critical maximum voltage. From VOUT_OV_FAULT_LIMIT
82 in[2-5]_lcrit_alarm Voltage critical low alarm. From VOLTAGE_UV_FAULT
84 in[2-5]_crit_alarm Voltage critical high alarm. From VOLTAGE_OV_FAULT
93 curr[2-5]_lcrit Critical minimum output current. From
95 curr[2-5]_crit Critical maximum current. From IOUT_OC_FAULT_LIMIT
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Dmax20751.rst53 in1_lcrit Critical minimum input voltage.
54 in1_crit Critical maximum input voltage.
56 in1_lcrit_alarm Input voltage critical low alarm.
64 in2_lcrit Critical minimum output voltage.
65 in2_crit Critical maximum output voltage.
67 in2_lcrit_alarm Output voltage critical low alarm.
78 temp1_crit Critical high temperature.
80 temp1_crit_alarm Chip temperature critical high alarm.
Dmax8688.rst52 in1_lcrit Critical minimum Voltage. VOUT_UV_FAULT_LIMIT register.
53 in1_crit Critical maximum voltage. From VOUT_OV_FAULT_LIMIT
57 in1_lcrit_alarm Voltage critical low alarm. From VOLTAGE_UV_FAULT
59 in1_crit_alarm Voltage critical high alarm. From VOLTAGE_OV_FAULT
67 curr1_crit Critical maximum current. From IOUT_OC_FAULT_LIMIT
70 curr1_crit_alarm Current critical high alarm. From IOUT_OC_FAULT status.
76 temp1_crit Critical high temperature. From OT_FAULT_LIMIT register.
80 temp1_crit_alarm Chip temperature critical high alarm. Set by comparing
Dpmbus.rst95 Each monitored channel has its own high and low limits, plus a critical
202 inX_lcrit Critical minimum Voltage.
204 inX_crit Critical maximum voltage.
208 inX_lcrit_alarm Voltage critical low alarm.
210 inX_crit_alarm Voltage critical high alarm.
221 currX_lcrit Critical minimum output current.
223 currX_crit Critical maximum current.
229 currX_lcrit_alarm Output current critical low alarm.
231 currX_crit_alarm Current critical high alarm.
243 powerX_crit Critical output power limit.
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Dina2xx.rst102 in0_lcrit Critical low shunt voltage
103 in0_crit Critical high shunt voltage
104 in0_lcrit_alarm Shunt voltage critical low alarm
105 in0_crit_alarm Shunt voltage critical high alarm
106 in1_lcrit Critical low bus voltage
107 in1_crit Critical high bus voltage
108 in1_lcrit_alarm Bus voltage critical low alarm
109 in1_crit_alarm Bus voltage critical high alarm
110 power1_crit Critical high power
111 power1_crit_alarm Power critical high alarm
Dmax16601.rst95 curr12_crit Critical output current.
96 curr12_crit_alarm Output current critical alarm.
128 curr21_crit Critical output current.
129 curr21_crit_alarm Output current critical alarm.
144 temp1_crit Critical high temperature.
145 temp1_crit_alarm Chip temperature critical high alarm.
155 temp6_crit Critical high temperature.
156 temp6_crit_alarm Chip temperature critical high alarm.
Dltc2978.rst253 in1_lcrit Critical minimum input voltage.
258 in1_crit Critical maximum input voltage.
267 in1_lcrit_alarm Input voltage critical low alarm.
272 in1_crit_alarm Input voltage critical high alarm.
300 in[N]_lcrit Critical minimum output voltage.
302 in[N]_crit Critical maximum output voltage.
308 in[N]_lcrit_alarm Output voltage critical low alarm.
310 in[N]_crit_alarm Output voltage critical high alarm.
343 temp[N]_lcrit Critical low temperature.
345 temp[N]_crit Critical high temperature.
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Dmax16064.rst52 in[1-4]_lcrit Critical minimum Voltage. VOUT_UV_FAULT_LIMIT register.
53 in[1-4]_crit Critical maximum voltage. From VOUT_OV_FAULT_LIMIT
57 in[1-4]_lcrit_alarm Voltage critical low alarm. From VOLTAGE_UV_FAULT
59 in[1-4]_crit_alarm Voltage critical high alarm. From VOLTAGE_OV_FAULT
66 temp1_crit Critical high temperature. From OT_FAULT_LIMIT register.
70 temp1_crit_alarm Chip temperature critical high alarm. Set by comparing
Dmax31785.rst44 in[1-6]_crit Critical maximum output voltage
45 in[1-6]_crit_alarm Output voltage critical high alarm
48 in[1-6]_lcrit Critical minimum output voltage
49 in[1-6]_lcrit_alarm Output voltage critical low alarm
61 temp[1-11]_crit Critical high temperature
62 temp[1-11]_crit_alarm Chip temperature critical high alarm
Ducd9000.rst97 in[1-12]_lcrit Critical minimum Voltage. VOUT_UV_FAULT_LIMIT register.
98 in[1-12]_crit Critical maximum voltage. From VOUT_OV_FAULT_LIMIT
102 in[1-12]_lcrit_alarm Voltage critical low alarm. From VOLTAGE_UV_FAULT
104 in[1-12]_crit_alarm Voltage critical high alarm. From VOLTAGE_OV_FAULT
110 curr[1-12]_lcrit Critical minimum output current. From
112 curr[1-12]_crit Critical maximum current. From IOUT_OC_FAULT_LIMIT
115 curr[1-12]_crit_alarm Current critical high alarm. From IOUT_OC_FAULT status.
124 temp[1-2]_crit Critical high temperature. From OT_FAULT_LIMIT register.
126 temp[1-2]_crit_alarm Temperature critical high alarm.
Dadt7410.rst54 exceeded, as well as a critical temperature (CT) pin to indicate that the
55 critical temperature set point has been exceeded. Both pins can be set up with a
75 maximum and critical temperature, it can only be set for temp#_max_hyst.
87 temp#_crit critical temperature setpoint
90 temp#_crit_hyst hysteresis for critical temperature (read-only)
93 temp#_crit_alarm critical temperature alarm flag
/Documentation/virt/
Dparavirt_ops.rst11 hypervisors. It allows each hypervisor to override critical operations and
16 corresponding to low level critical instructions and high level
18 time by enabling binary patching of the low-ops critical operations
28 Usually these operations correspond to low level critical instructions. They
29 are called frequently and are performance critical. The overhead is
35 them are very performance critical.
/Documentation/locking/
Dseqlock.rst15 read side critical section is even and the same sequence count value is
16 read again at the end of the critical section. The data in the set must
17 be copied out inside the read side critical section. If the sequence
18 count has changed between the start and the end of the critical section,
22 critical section. After starting the critical section the sequence count
24 the end of the write side critical section the sequence count becomes
27 A sequence counter write side critical section must never be preempted
43 multiple writers. Write side critical sections must thus be serialized
76 /* ... [[write-side critical section]] ... */
85 /* ... [[read-side critical section]] ... */
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/Documentation/RCU/
Dlockdep.rst9 critical section. Each flavor of RCU is tracked separately (but note
31 Check for RCU read-side critical section.
33 Check for RCU-bh read-side critical section.
35 Check for RCU-sched read-side critical section.
37 Check for SRCU read-side critical section.
80 1. An RCU read-side critical section (implicit), or
85 RCU read-side critical sections, in case (2) the ->file_lock prevents
96 complain if this was used in an RCU read-side critical section unless one
105 critical section. However, a lockdep expression can be passed to them
108 false and they are called from outside any RCU read-side critical section.
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DwhatisRCU.rst95 critical sections.
157 entering an RCU read-side critical section. It is illegal
158 to block while in an RCU read-side critical section, though
160 read-side critical sections. Any RCU-protected data structure
161 accessed during an RCU read-side critical section is guaranteed to
162 remain unreclaimed for the full duration of that critical section.
171 exiting an RCU read-side critical section. Note that RCU
172 read-side critical sections may be nested and/or overlapping.
180 read-side critical sections on all CPUs have completed.
182 any subsequent RCU read-side critical sections to complete.
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/Documentation/devicetree/bindings/thermal/
Dbrcm,sr-thermal.txt41 type = "critical";
53 type = "critical";
65 type = "critical";
77 type = "critical";
89 type = "critical";
101 type = "critical";
/Documentation/litmus-tests/rcu/
DRCU+sync+read.litmus7 * sees all stores done in prior RCU read-side critical sections. Such
8 * read-side critical sections would have ended before the grace period ended.
11 * other things) that an RCU read-side critical section cannot span a grace period.

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