Searched full:definition (Results 1 – 25 of 361) sorted by relevance
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| /Documentation/devicetree/bindings/sound/ |
| D | qcom,wcd9335.txt | 14 Definition: For SLIMbus interface it should be "slimMID,PID",
24 Definition: Should be ('Device index', 'Instance ID')
29 Definition: Interrupts via WCD INTR1 and INTR2 pins
34 Definition: Interrupt names of WCD INTR1 and INTR2
40 Definition: Reset gpio line
45 Definition: SLIM interface device
50 Definition: See clock-bindings.txt section "consumers". List of
56 Definition: Must contain "mclk", "mclk2" and "slimbus" strings.
61 Definition: Should contain a reference to the 1.8V buck supply
66 Definition: Should contain a reference to the 1.8V SIDO buck supply
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| D | qcom,sdm845.txt | 8 Definition: must be one of this
16 Definition: A list of the connections between audio components.
25 Definition: The user-visible name of this sound card.
30 Definition: A list of phandles for auxiliary devices (e.g. analog
42 Definition: User friendly name for dai link
48 Definition: cpu dai sub-node
53 Definition: codec dai sub-node
58 Definition: platform dai sub-node
63 Definition: dai phandle/s and port of CPU/CODEC/PLATFORM node.
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | qcom,hexagon-v56.txt | 9 Definition: must be one of:
16 Definition: must specify the base address and size of the qdsp6ss register
21 Definition: must list the watchdog, fatal IRQs ready, handover and
27 Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack"
32 Definition: List of phandles and clock specifier pairs for the Hexagon,
38 Definition: List of clock input name strings sorted in the same
39 order as the clocks property. Definition must have
47 Definition: List of clock input name strings sorted in the same
48 order as the clocks property. Definition must have
55 Definition: reference to cx power domain node.
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| D | qcom,q6v5.txt | 9 Definition: must be one of:
22 Definition: must specify the base address and size of the qdsp6 and
28 Definition: must be "q6dsp" and "rmb"
33 Definition: reference to the interrupts that match interrupt-names
38 Definition: The interrupts needed depends on the the compatible
55 Definition: must list the relative firmware image paths for mba and
62 Definition: reference to the clocks that match clock-names
67 Definition: The clocks needed depend on the compatible string:
90 Definition: reference to the reset-controller for the modem sub-system
99 Definition: must be "mss_restart" for the modem sub-system
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| D | qcom,wcnss-pil.txt | 9 Definition: must be one of:
17 Definition: must specify the base address and size of the CCU, DXE and
23 Definition: must be "ccu", "dxe", "pmu"
28 Definition: must list the watchdog and fatal IRQs and may specify the
34 Definition: should be "wdog", "fatal", optionally followed by "ready",
42 Definition: reference to the regulators to be held on behalf of the
48 Definition: reference to the SMEM state used to indicate to WCNSS that
54 Definition: should be "stop"
59 Definition: reference to reserved-memory node for the remote processor
69 Definition: must be one of:
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| /Documentation/devicetree/bindings/pci/ |
| D | qcom,pcie.txt | 6 Definition: Value should contain
20 Definition: Register ranges as listed in the reg-names property
25 Definition: Must include the following entries
34 Definition: Should be "pci". As specified in designware-pcie.txt
39 Definition: Should be 3. As specified in designware-pcie.txt
44 Definition: Should be 2. As specified in designware-pcie.txt
49 Definition: As specified in designware-pcie.txt
54 Definition: MSI interrupt
59 Definition: Should contain "msi"
64 Definition: Should be 1. As specified in designware-pcie.txt
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | qcom,mdm9615-pinctrl.txt | 9 Definition: must be "qcom,mdm9615-pinctrl"
14 Definition: the base address and size of the TLMM register space.
19 Definition: should specify the TLMM summary IRQ.
24 Definition: identifies this node as an interrupt controller
29 Definition: must be 2. Specifying the pin number and flags, as defined
35 Definition: identifies this node as a gpio controller
40 Definition: must be 2. Specifying the pin number and flags, as defined
45 Definition: see ../gpio/gpio.txt
49 Definition: see ../gpio/gpio.txt
83 Definition: List of gpio pins affected by the properties specified in
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| D | qcom,pmic-mpp.txt | 9 Definition: Should contain one of:
30 Definition: Register base of the MPP block and length.
35 Definition: Must contain an array of encoded interrupt specifiers for
41 Definition: Mark the device node as a GPIO controller
46 Definition: Must be 2;
80 Definition: List of MPP pins affected by the properties specified in
92 Definition: Specify the alternative function to be configured for the
101 Definition: The specified pins should be configured as no pull.
106 Definition: The specified pins should be configured as pull up.
115 Definition: The specified pins will put in high-Z mode and disabled.
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| D | qcom,msm8960-pinctrl.txt | 9 Definition: must be "qcom,msm8960-pinctrl"
14 Definition: the base address and size of the TLMM register space.
19 Definition: should specify the TLMM summary IRQ.
24 Definition: identifies this node as an interrupt controller
29 Definition: must be 2. Specifying the pin number and flags, as defined
35 Definition: identifies this node as a gpio controller
40 Definition: must be 2. Specifying the pin number and flags, as defined
45 Definition: see ../gpio/gpio.txt
49 Definition: see ../gpio/gpio.txt
83 Definition: List of gpio pins affected by the properties specified in
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| D | qcom,msm8976-pinctrl.txt | 9 Definition: must be "qcom,msm8976-pinctrl"
14 Definition: the base address and size of the TLMM register space.
19 Definition: should specify the TLMM summary IRQ.
24 Definition: identifies this node as an interrupt controller
29 Definition: must be 2. Specifying the pin number and flags, as defined
35 Definition: identifies this node as a gpio controller
40 Definition: must be 2. Specifying the pin number and flags, as defined
45 Definition: see ../gpio/gpio.txt
49 Definition: see ../gpio/gpio.txt
83 Definition: List of gpio pins affected by the properties specified in
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| D | qcom,apq8084-pinctrl.txt | 9 Definition: must be "qcom,apq8084-pinctrl"
14 Definition: the base address and size of the TLMM register space.
19 Definition: should specify the TLMM summary IRQ.
24 Definition: identifies this node as an interrupt controller
29 Definition: must be 2. Specifying the pin number and flags, as defined
35 Definition: identifies this node as a gpio controller
40 Definition: must be 2. Specifying the pin number and flags, as defined
45 Definition: see ../gpio/gpio.txt
49 Definition: see ../gpio/gpio.txt
83 Definition: List of gpio pins affected by the properties specified in
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| D | qcom,ipq8074-pinctrl.txt | 9 Definition: must be "qcom,ipq8074-pinctrl"
14 Definition: the base address and size of the TLMM register space.
19 Definition: should specify the TLMM summary IRQ.
24 Definition: identifies this node as an interrupt controller
29 Definition: must be 2. Specifying the pin number and flags, as defined
35 Definition: identifies this node as a gpio controller
40 Definition: must be 2. Specifying the pin number and flags, as defined
45 Definition: see ../gpio/gpio.txt
49 Definition: see ../gpio/gpio.txt
83 Definition: List of gpio pins affected by the properties specified in
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| D | qcom,sc7180-pinctrl.txt | 9 Definition: must be "qcom,sc7180-pinctrl"
14 Definition: the base address and size of the north, south and west
20 Definition: names for the cells of reg, must contain "north", "south"
26 Definition: should specify the TLMM summary IRQ.
31 Definition: identifies this node as an interrupt controller
36 Definition: must be 2. Specifying the pin number and flags, as defined
42 Definition: identifies this node as a gpio controller
47 Definition: must be 2. Specifying the pin number and flags, as defined
53 Definition: see ../gpio/gpio.txt
58 Definition: see ../gpio/gpio.txt
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| D | qcom,pmic-gpio.txt | 9 Definition: must be one of:
39 Definition: Register base of the GPIO block and length.
44 Definition: Must contain an array of encoded interrupt specifiers for
50 Definition: Mark the device node as a GPIO controller
55 Definition: Must be 2;
90 Definition: List of gpio pins affected by the properties specified in
117 Definition: Specify the alternative function to be configured for the
134 Definition: The specified pins should be configured as no pull.
139 Definition: The specified pins should be configured as pull down.
144 Definition: The specified pins should be configured as pull up.
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| D | qcom,msm8998-pinctrl.txt | 9 Definition: must be "qcom,msm8998-pinctrl"
14 Definition: the base address and size of the TLMM register space.
19 Definition: should specify the TLMM summary IRQ.
24 Definition: identifies this node as an interrupt controller
29 Definition: must be 2. Specifying the pin number and flags, as defined
35 Definition: identifies this node as a gpio controller
40 Definition: must be 2. Specifying the pin number and flags, as defined
45 Definition: see ../gpio/gpio.txt
49 Definition: see ../gpio/gpio.txt
83 Definition: List of gpio pins affected by the properties specified in
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| D | qcom,msm8994-pinctrl.txt | 9 Definition: Should contain one of:
16 Definition: the base address and size of the TLMM register space.
21 Definition: should specify the TLMM summary IRQ.
26 Definition: identifies this node as an interrupt controller
31 Definition: must be 2. Specifying the pin number and flags, as defined
37 Definition: identifies this node as a gpio controller
42 Definition: must be 2. Specifying the pin number and flags, as defined
47 Definition: see ../gpio/gpio.txt
51 Definition: see ../gpio/gpio.txt
85 Definition: List of gpio pins affected by the properties specified in
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| D | qcom,msm8916-pinctrl.txt | 9 Definition: must be "qcom,msm8916-pinctrl"
14 Definition: the base address and size of the TLMM register space.
19 Definition: should specify the TLMM summary IRQ.
24 Definition: identifies this node as an interrupt controller
29 Definition: must be 2. Specifying the pin number and flags, as defined
35 Definition: identifies this node as a gpio controller
40 Definition: must be 2. Specifying the pin number and flags, as defined
45 Definition: see ../gpio/gpio.txt
49 Definition: see ../gpio/gpio.txt
83 Definition: List of gpio pins affected by the properties specified in
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| D | qcom,sm8150-pinctrl.txt | 9 Definition: must be "qcom,sm8150-pinctrl"
14 Definition: the base address and size of the north, south, west
26 Definition: should specify the TLMM summary IRQ.
31 Definition: identifies this node as an interrupt controller
36 Definition: must be 2. Specifying the pin number and flags, as defined
42 Definition: identifies this node as a gpio controller
47 Definition: must be 2. Specifying the pin number and flags, as defined
53 Definition: see ../gpio/gpio.txt
58 Definition: see ../gpio/gpio.txt
92 Definition: List of gpio pins affected by the properties specified in
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| /Documentation/devicetree/bindings/phy/ |
| D | qcom,usb-8x16-phy.txt | 6 Definition: Should contain "qcom,usb-8x16-phy".
11 Definition: USB PHY base address and length of the register map
16 Definition: See clock-bindings.txt section "consumers". List of
23 Definition: Must contain "iface" and "core" strings.
28 Definition: phandle to the regulator VDCCX supply node.
33 Definition: phandle to the regulator 1.8V supply node.
38 Definition: phandle to the regulator 3.3V supply node.
43 Definition: See reset.txt section "consumers". PHY reset specifier.
48 Definition: Must contain "phy" string.
53 Definition: Some boards are using Dual SPDT USB Switch, witch is
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| D | qcom,usb-hs-phy.txt | 8 Definition: Should contain "qcom,usb-hs-phy" and more specifically one of the
18 Definition: Should contain 0
23 Definition: Should contain clock specifier for the reference and sleep
29 Definition: Should contain "ref" and "sleep" for the reference and sleep
35 Definition: Should contain the phy and POR resets
40 Definition: Should contain "phy" and "por" for the phy and POR resets
46 Definition: Should contain a reference to the 3.3V supply
51 Definition: Should contain a reference to the 1.8V supply
56 Definition: Should contain the vbus extcon
61 Definition: Should contain a sequence of ULPI address and value pairs to
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| /Documentation/devicetree/bindings/input/ |
| D | qcom,pm8xxx-keypad.txt | 8 Definition: must be one of:
15 Definition: address of keypad control register
20 Definition: the first interrupt specifies the key sense interrupt
28 Definition: the linux keymap. More information can be found in
34 Definition: don't enable autorepeat feature.
39 Definition: use any event on keypad as wakeup event.
45 Definition: number of rows in the keymap. More information can be found
51 Definition: number of columns in the keymap. More information can be
57 Definition: time in microseconds that key must be pressed or release
63 Definition: time in microseconds to pause between successive scans
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| /Documentation/devicetree/bindings/soundwire/ |
| D | qcom,sdw.txt | 10 Definition: must be "qcom,soundwire-v<MAJOR>.<MINOR>.<STEP>",
19 Definition: the base address and size of SoundWire controller
25 Definition: should specify the SoundWire Controller IRQ
30 Definition: should be "iface" for SoundWire Controller interface clock
35 Definition: should specify the SoundWire Controller interface clock
40 Definition: must be 1 for digital audio interfaces on the controller.
45 Definition: must be count of data out ports
50 Definition: must be count of data in ports
55 Definition: should specify payload transport window offset1 of each
62 Definition: should specify payload transport window offset2 of each
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| /Documentation/devicetree/bindings/mfd/ |
| D | qcom-pm8xxx.txt | 11 Definition: must be one of:
19 Definition: must be 1
24 Definition: must be 0
29 Definition: specifies the interrupt that indicates a subdevice
37 Definition: must be 2. Specifies the number of cells needed to encode
50 Definition: identifies this node as an interrupt controller
62 Definition: must be one of:
71 Definition: single entry specifying the base address of the RTC registers
76 Definition: single entry specifying the RTC's alarm interrupt
81 Definition: indicates that the setting of RTC time is allowed by
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| /Documentation/devicetree/bindings/power/avs/ |
| D | qcom,cpr.txt | 13 Definition: should be "qcom,qcs404-cpr", "qcom,cpr" for qcs404
18 Definition: base address and size of the rbcpr register region
23 Definition: should specify the CPR interrupt
28 Definition: phandle to the reference clock
33 Definition: must be "ref"
38 Definition: phandle to the vdd-apc-supply regulator
43 Definition: should be 0
48 Definition: A phandle to the OPP table containing the
55 Definition: phandle to syscon for writing ACC settings
60 Definition: phandle to nvmem cells containing the data
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,smp2p.txt | 12 Definition: must be one of:
18 Definition: one entry specifying the smp2p notification interrupt
23 Definition: reference to the associated doorbell in APCS, as described
29 Definition: three entries specifying the outgoing ipc bit used for
38 Definition: two identifiers of the inbound and outbound smem items used
44 Definition: specifies the identifier of the local endpoint of this edge
49 Definition: specifies the identifier of the remote endpoint of this edge
59 Definition: specifies the name of this entry, for inbound entries this
67 Definition: marks the entry as inbound; the node should be specified
75 Definition: must be 2 - denoting the bit in the entry and IRQ flags
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