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/Documentation/networking/
Dsecid.rst13 If this is an outbound flow, the label is derived from the socket, if any, or
16 derived from other sources such as process context, device, etc., in special
19 If this is an inbound flow, the label is derived from the IPSec security
/Documentation/hwmon/
Dmax16601.rst58 curr1_input VCORE input current, derived from duty cycle and output
88 curr10_input VCORE input current, derived from sensor element.
134 power1_input Input power, derived from duty cycle and output current.
138 power2_input Input power, derived from input current sensor.
Dg760a.rst29 The measured fan rotation speed returned via 'fan1_input' is derived
Dthmc50.rst25 This driver was derived from the 2.4 kernel thmc50.c source file.
Dlm73.rst81 Mathematically, the resolution can be derived from the conversion time
/Documentation/devicetree/bindings/clock/
Dmvebu-core-clock.txt43 2 = l2clk (L2 Cache clock derived from CPU0 clock)
44 3 = ddrclk (DDR controller clock derived from CPU0 clock)
49 2 = ddrclk (DDR controller clock derived from CPU0 clock)
Drockchip,rv1108-cru.txt35 - "hdmiphy" - external clock input derived from HDMI PHY - optional
36 - "usbphy" - external clock input derived from USB PHY - optional
Dingenic,cgu.yaml12 to provide many different clock signals derived from only 2 external source
Dbrcm,iproc-clocks.txt8 LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
50 ASIU clocks are a special case. These clocks are derived directly from the
/Documentation/devicetree/bindings/mtd/
Dvf610-nfc.txt13 - assigned-clock-rates: The NAND bus timing is derived from this clock
15 in a board stuffing. Typical NAND memory timings derived from this
/Documentation/devicetree/bindings/sound/
Dcdns,xtfpga-i2s.txt8 is derived from it.
Dfsl,esai.txt32 "fsys" The system clock derived from ahb clock used to
/Documentation/fb/
Dmatroxfb.rst261 xres:X horizontal resolution, in pixels. Default is derived from `vesa`
263 yres:X vertical resolution, in pixel lines. Default is derived from `vesa`
266 pixel line of picture. Default is derived from `vesa` option.
268 pulse. Default is derived from `vesa` option.
269 vslen:X length of VSYNC pulse, in lines. Default is derived from `vesa`
272 Default is derived from `vesa` option.
274 pulse. Default is derived from `vesa` option.
275 hslen:X length of HSYNC pulse, in pixels. Default is derived from `vesa`
277 pixclock:X dotclocks, in ps (picoseconds). Default is derived from `vesa`
299 70 for modes derived from `vesa` with yres <= 400, 60Hz for
/Documentation/devicetree/bindings/gpio/
Dgpio-samsung.txt10 should be the following with values derived from the SoC user manual.
/Documentation/devicetree/bindings/timer/
Dnvidia,tegra210-timer.txt4 timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived
/Documentation/usb/
Dohci.rst7 The "ohci-hcd" driver is a USB Host Controller Driver (HCD) that is derived
/Documentation/devicetree/bindings/hwmon/
Dgpio-fan.txt17 min and max states are derived from the speed-map of the fan.
/Documentation/sound/soc/
Dclocking.rst13 or SYSCLK). This audio master clock can be derived from a number of sources
/Documentation/devicetree/bindings/dma/
Drenesas,nbpfaxi.txt36 won't be used, this information is derived from the compatibility string.
/Documentation/driver-api/nfc/
Dnfc-pn544.rst22 In the normal (HCI) mode the protocol used is derived from the ETSI
/Documentation/powerpc/
Dkaslr-booke32.rst20 Entropy is derived from the banner and timer base, which will change every
/Documentation/devicetree/bindings/serial/
Dmtk-uart.txt38 - "baud": The clock the baudrate is derived from
/Documentation/scsi/
DLICENSE.FlashPoint47 products derived from this software without specific prior written
/Documentation/security/keys/
Decryptfs.rst11 using a key, the FEKEK, derived from a user prompted passphrase; in the latter
/Documentation/admin-guide/perf/
Darm-cmn.rst44 "nodeid" to the appropriate value derived from the CMN configuration

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