Searched full:describes (Results 1 – 25 of 573) sorted by relevance
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| /Documentation/devicetree/bindings/clock/ti/davinci/ |
| D | pll.txt | 26 Describes the main PLL clock output (before POSTDIV). The node name must
33 Describes the PLLDIVn divider clocks that provide the SYSCLKn clock
41 Describes the AUXCLK output of the PLL. The node name must be "auxclk".
48 Describes the OBSCLK output of the PLL. The node name must be "obsclk".
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| /Documentation/devicetree/bindings/x86/ |
| D | ce4100.txt | 30 A "cpu" node describes one logical processor (hardware thread).
44 This node describes the in-core peripherals. Required property:
49 This node describes the PCI bus on the SoC. Its property should be
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| /Documentation/devicetree/bindings/powerpc/ |
| D | ibm,powerpc-cpu-features.txt | 12 This device tree binding describes CPU features available to software, with
104 This property describes the privilege levels and/or software components
118 This property describes the HV privilege support required to enable the
137 This property describes the OS privilege support required to enable the
154 property describes the bit number in the HFSCR register that the
167 property describes the bit number in the FSCR register that the
180 This property describes the bit number that should be set in the ELF AUX
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| /Documentation/devicetree/bindings/net/ |
| D | marvell-orion-net.txt | 9 first level describes the ethernet controller itself and the second level
10 describes up to 3 ethernet port nodes within that controller. The reason for
12 set of controller registers. Each port node describes port-specific properties.
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| D | marvell,prestera.txt | 36 - ranges: describes the address mapping of a memory-mapped bus.
53 - base-mac-provider: describes handle to node which provides base mac address,
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| /Documentation/devicetree/bindings/c6x/ |
| D | dscr.txt | 64 This property describes the bitfields used to control the state of devices.
65 Each tuple describes a range of identical bitfields used to control one or
80 This property describes the bitfields used to provide device state status
81 for device states controlled by the DSCR. Each tuple describes a range of
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| /Documentation/arm/ |
| D | setup.rst | 5 The following document describes the kernel initialisation parameter
55 This describes the character position of cursor on VGA console, and
85 This describes the kernel virtual start address and size of the
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| /Documentation/ABI/testing/ |
| D | sysfs-hypervisor-xen | 17 Describes mode that Xen's performance-monitoring unit (PMU)
35 Describes Xen PMU features (as an integer). A set bit indicates
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| D | sysfs-bus-i3c | 53 This entry describes the BCR of the master controller driving
63 This entry describes the DCR of the master controller driving
75 This entry describes the PID of the master controller driving
88 This entry describes the HDRCAP of the master controller
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| D | sysfs-devices-firmware_node | 14 that describes the device as provided by the _STR method in the ACPI
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| /Documentation/admin-guide/perf/ |
| D | imx-ddr.rst | 16 The "format" directory describes format of the config (event ID) and config1
18 devices/imx8_ddr0/format/. The "events" directory describes the events types
20 devices/imx8_ddr0/events/. The "caps" directory describes filter features implemented
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| /Documentation/devicetree/bindings/gpio/ |
| D | nvidia,tegra186-gpio.txt | 6 differences. Hence, this document describes closely related but different
30 Tegra HW documentation describes a unified naming convention for all GPIOs
43 describes the port-level mapping. In that file, the naming convention for ports
92 order the HW manual describes them. The number of entries required varies
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| /Documentation/devicetree/bindings/input/touchscreen/ |
| D | ts4800-ts.txt | 8 describes the FPGA's syscon registers.
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| /Documentation/devicetree/bindings/phy/ |
| D | socionext,uniphier-usb3ss-phy.yaml | 10 This describes the devicetree bindings for PHY interfaces built into
13 this describes about Super-Speed PHY.
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| D | socionext,uniphier-usb3hs-phy.yaml | 10 This describes the devicetree bindings for PHY interfaces built into
13 this describes about High-Speed PHY.
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| /Documentation/devicetree/bindings/arm/freescale/ |
| D | fsl,vf610-mscm-cpucfg.txt | 3 The MSCM IP contains multiple sub modules, this binding describes the first
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| /Documentation/devicetree/bindings/power/supply/ab8500/ |
| D | chargalg.txt | 3 The properties below describes the node for chargalg driver.
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| D | btemp.txt | 3 The properties below describes the node for btemp driver.
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| /Documentation/firmware-guide/ |
| D | index.rst | 7 This section describes the ACPI subsystem in Linux from firmware perspective.
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| /Documentation/filesystems/ext4/ |
| D | checksums.rst | 26 The following table describes the data elements that go into each type
27 of checksum. The checksum function is whatever the superblock describes
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| /Documentation/networking/ |
| D | nf_flowtable.rst | 7 This documentation describes the software flowtable infrastructure available in
34 This is represented in Fig.1, which describes the classic forwarding path
111 acceleration" that describes how things were before this infrastructure was
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| /Documentation/admin-guide/hw-vuln/ |
| D | index.rst | 5 This section describes CPU vulnerabilities and provides an overview of the
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| /Documentation/devicetree/bindings/display/imx/ |
| D | ldb.txt | 48 or a display-timings node that describes the video timings for the connected
66 - display-timings : A node that describes the display timings as defined in
69 This describes how the color bits are laid out in the
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| /Documentation/devicetree/bindings/watchdog/ |
| D | ts4800-wdt.txt | 6 describes the FPGA's syscon registers.
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| /Documentation/devicetree/bindings/timer/ |
| D | ti,c64x+timer64.txt | 4 The timer64 node describes C6X event timers.
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