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/Documentation/devicetree/bindings/display/
Dallwinner,sun4i-a10-display-engine.yaml4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-engine.yaml#
7 title: Allwinner A10 Display Engine Pipeline Device Tree Bindings
14 The display engine pipeline (and its entry point, since it can be
18 The Allwinner A10 Display pipeline is composed of several components
22 display pipeline, when there are multiple components of the same
52 - allwinner,sun4i-a10-display-engine
53 - allwinner,sun5i-a10s-display-engine
54 - allwinner,sun5i-a13-display-engine
55 - allwinner,sun6i-a31-display-engine
56 - allwinner,sun6i-a31s-display-engine
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Dcirrus,clps711x-fb.txt8 - display : phandle to a display node as described in
9 Documentation/devicetree/bindings/display/panel/display-timing.txt.
10 Additionally, the display node has to define properties:
25 display = <&display>;
28 display: display {
33 display-timings {
Dallwinner,sun4i-a10-display-frontend.yaml4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-frontend.yaml#
7 title: Allwinner A10 Display Engine Frontend Device Tree Bindings
14 The display engine frontend does formats conversion, scaling,
20 - allwinner,sun4i-a10-display-frontend
21 - allwinner,sun5i-a13-display-frontend
22 - allwinner,sun6i-a31-display-frontend
23 - allwinner,sun7i-a20-display-frontend
24 - allwinner,sun8i-a23-display-frontend
25 - allwinner,sun8i-a33-display-frontend
26 - allwinner,sun9i-a80-display-frontend
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Dsimple-framebuffer.yaml4 $id: http://devicetree.org/schemas/display/simple-framebuffer.yaml#
15 the bootloader, with the assumption that the display hardware has
23 If the devicetree contains nodes for the display hardware used by a
25 display, which contains a phandle pointing to the primary display
30 It is advised to add display# aliases to help the OS determine how
31 to number things. If display# aliases are used, then if the simplefb
32 node contains a display property then the /aliases/display# path
33 must point to the display hw node the display property points to,
38 to it, or to the primary display hw node, as with display#
39 aliases. If display aliases are used then it should be set to the
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Dallwinner,sun4i-a10-display-backend.yaml4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-backend.yaml#
7 title: Allwinner A10 Display Engine Backend Device Tree Bindings
14 The display engine backend exposes layers and sprites to the system.
19 - allwinner,sun4i-a10-display-backend
20 - allwinner,sun5i-a13-display-backend
21 - allwinner,sun6i-a31-display-backend
22 - allwinner,sun7i-a20-display-backend
23 - allwinner,sun8i-a23-display-backend
24 - allwinner,sun8i-a33-display-backend
25 - allwinner,sun9i-a80-display-backend
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Drepaper.txt4 - compatible: "pervasive,e1144cs021" for 1.44" display
5 "pervasive,e1190cs021" for 1.9" display
6 "pervasive,e2200cs021" for 2.0" display
7 "pervasive,e2271cs021" for 2.7" display
32 display {
51 pervasive,thermal-zone = "display";
Dmxsfb.txt23 lcdif1: display-controller@2220000 {
46 - display: phandle to display node (see below for details)
48 * display node
55 - display-timings: Refer to binding doc display-timing.txt for details.
64 display: display {
68 display-timings {
Datmel,lcdc.txt17 - display: a phandle pointing to the display node
20 - display: a display node is required to initialize the lcd panel
22 - default-mode: a videomode within the display with timing parameters
36 display = <&display0>;
50 Atmel LCDC Display
66 display0: display {
74 display-timings {
Dssd1307fb.txt17 - reset-gpios: The GPIO used to reset the OLED display, if available. See
20 - solomon,segment-no-remap: Display needs normal (non-inverted) data column
23 - solomon,com-seq: Display uses sequential COM pin configuration
24 - solomon,com-lrremap: Display uses left-right COM pin remap
25 - solomon,com-invdir: Display uses inverted COM pin scan direction
26 - solomon,com-offset: Number of the COM pin wired to the first display line
38 - solomon,area-color-enable: Display uses color mode
39 - solomon,low-power. Display runs in low power mode
/Documentation/gpu/
Damdgpu-dc.rst2 drm/amd/display - Display Core (DC)
7 Because it is partially shared with other operating systems, the Display Core
10 1. **Display Core (DC)** contains the OS-agnostic components. Things like
12 2. **Display Manager (DM)** contains the OS-dependent components. Hooks to the
24 ``Display Core initialized with <version number here>``
26 AMDgpu Display Manager
29 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
32 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
38 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
41 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
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Di915.rst6 models) integrated GFX chipsets with both Intel display and rendering
13 This section covers core driver infrastructure used by both the display
67 Display Hardware Handling
70 This section covers everything related to the display hardware including
72 display, output probing and related topics.
79 its own tailor-made infrastructure for executing a display configuration
85 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c
88 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.h
91 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c
94 Display FIFO Underrun Reporting
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Dtegra.rst2 drm/tegra NVIDIA Tegra GPU and display driver
5 NVIDIA Tegra SoCs support a set of display, graphics and video functions via
21 - A KMS driver that supports the display controllers as well as a number of
64 The display hardware has remained mostly backwards compatible over the various
68 Display Controllers
71 Tegra SoCs have two display controllers, each of which can be associated with
72 zero or more outputs. Outputs can also share a single display controller, but
73 only if they run with compatible display timings. Two display controllers can
75 on two outputs don't match. A display controller is modelled as a CRTC in KMS
78 On Tegra186, the number of display controllers has been increased to three. A
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/Documentation/userspace-api/media/v4l/
Dext-ctrls-colorimetry.rst49 The mastering display defines the color volume (the color primaries,
50 white point and luminance range) of a display considered to be the
51 mastering display for the current video content.
65 primary component c of the mastering display in increments of 0.00002.
66 For describing the mastering display that uses Red, Green and Blue
73 primary component c of the mastering display in increments of 0.00002.
74 For describing the mastering display that uses Red, Green and Blue
81 point of the mastering display in increments of 0.00002.
85 point of the mastering display in increments of 0.00002.
88 - Specifies the nominal maximum display luminance of the mastering
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/Documentation/devicetree/bindings/display/rockchip/
Drockchip-drm.yaml4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-drm.yaml#
15 vop devices or other display interface nodes that comprise the
20 const: rockchip,display-subsystem
25 Should contain a list of phandles pointing to display interface port
27 Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml
37 display-subsystem {
38 compatible = "rockchip,display-subsystem";
/Documentation/devicetree/bindings/display/panel/
Ddisplay-timings.yaml4 $id: http://devicetree.org/schemas/display/panel/display-timings.yaml#
7 title: display timings bindings
15 A display panel may be able to handle several display timings,
17 The display-timings node makes it possible to specify the timings
18 and to specify the timing that is native for the display.
22 const: display-timings
27 The default display timing is the one specified as native-mode.
47 display-timings {
Dpanel-simple.yaml4 $id: http://devicetree.org/schemas/display/panel/panel-simple.yaml#
17 The panel may use an OF graph binding for the association to the display,
18 or it may be a direct child node of the display.
104 # DLC Display Co. DLC1010GIG 10.1" WXGA TFT LCD Panel
106 # Emerging Display Technology Corp. 3.5" QVGA TFT LCD panel
108 # Emerging Display Technology Corp. 480x272 TFT Display with capacitive touch
110 # Emerging Display Technology Corp. 480x272 TFT Display
112 # Emerging Display Technology Corp. 5.7" VGA TFT LCD panel
114 # Emerging Display Technology Corp. WVGA TFT Display with capacitive touch
116 # Emerging Display Technology Corp. WVGA TFT Display with capacitive touch
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Dpanel-common.yaml4 $id: http://devicetree.org/schemas/display/panel/panel-common.yaml#
7 title: Common Properties for Display Panels
15 display panels. It doesn't constitue a device tree binding specification by
50 Display rotation in degrees counter clockwise (0,90,180,270)
54 # Display Timings
57 Most display panels are restricted to a single resolution and
58 require specific display timings. The panel-timing subnode expresses those
62 display-timings:
64 Some display panels support several resolutions with different timings.
65 The display-timings bindings supports specifying several timings and
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/Documentation/devicetree/bindings/auxdisplay/
Dhit,hd44780.yaml14 LCDs that can display one or more lines of text. It exposes an M6800 bus
51 display-height-chars:
52 description: Height of the display, in character cells,
57 display-width-chars:
58 description: Width of the display, in character cells.
66 display-width-chars for displays with more than 2 lines).
76 - display-height-chars
77 - display-width-chars
94 display-height-chars = <2>;
95 display-width-chars = <16>;
/Documentation/devicetree/bindings/display/imx/
Dfsl,imx-fb.txt11 - display: Phandle to a display node as described in
12 Documentation/devicetree/bindings/display/panel/display-timing.txt
13 Additional, the display node has to define properties:
16 A display node may optionally define
34 display = <&display0>;
43 display-timings {
Dldb.txt1 Device-Tree bindings for LVDS Display Bridge (ldb)
3 LVDS Display Bridge
6 The LVDS Display Bridge device tree node contains up to two lvds-channel
14 multiplexer in the front to select any of the four IPU display
20 the display interface selector clocks, as described in
48 or a display-timings node that describes the video timings for the connected
49 LVDS display as well as the fsl,data-mapping and fsl,data-width properties.
62 display-timings are used instead.
64 Optional properties (required if display-timings are used):
66 - display-timings : A node that describes the display timings as defined in
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Dfsl-imx-drm.txt5 IPU or other display interface nodes that comprise the graphics subsystem.
8 - compatible: Should be "fsl,imx-display-subsystem"
9 - ports: Should contain a list of phandles pointing to display interface ports
14 display-subsystem {
15 compatible = "fsl,display-subsystem";
113 Parallel display support
117 - compatible: Should be "fsl,imx-parallel-display"
119 - interface-pix-fmt: How this display is connected to the
120 display interface. Currently supported types: "rgb24", "rgb565", "bgr666"
122 - edid: verbatim EDID data block describing attached display.
[all …]
Dnxp,imx8mq-dcss.yaml5 $id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#"
8 title: iMX8MQ Display Controller Subsystem (DCSS)
15 The DCSS (display controller sub system) is used to source up to three
16 display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP
44 - description: Display APB clock for all peripheral PIO access interfaces
45 - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
79 A port node pointing to the input port of a HDMI/DP or MIPI display bridge.
86 dcss: display-controller@32e00000 {
/Documentation/ABI/testing/
Dsysfs-platform-asus-laptop1 What: /sys/devices/platform/asus_laptop/display
6 This file allows display switching. The value
16 - 0 (0000b) means no display
32 Some models like the W1N have a LED display that can be
33 used to display several items of information.
34 To control the LED display, use the following::
38 where T control the 3 letters display, and DDD the 3 digits display.
/Documentation/devicetree/bindings/clock/
Dfsl,plldig.yaml7 title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding
13 NXP LS1028A has a clock domain PXLCLK0 used for the Display output
14 interface in the display core, as implemented in TSMC CLN28HPM PLL.
15 which generate and offers pixel clocks to Display.
49 # Display PIXEL Clock node:
51 dpclk: clock-display@f1f0000 {
/Documentation/devicetree/bindings/powerpc/fsl/
Ddiu.txt1 * Freescale Display Interface Unit
13 - edid : verbatim EDID data block describing attached display.
15 program the display controller.
18 display@2c000 {
26 display@2100 {

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