Searched full:divider (Results 1 – 25 of 89) sorted by relevance
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| /Documentation/devicetree/bindings/iio/afe/ |
| D | voltage-divider.txt | 1 Voltage divider
4 When an io-channel measures the midpoint of a voltage divider, the
6 of the divider. This binding describes the voltage divider in such
24 - compatible : "voltage-divider"
28 - full-ohms : Resistance R + Rout for the full divider. The io-channel
33 voltage divider (R = 200 Ohms, Rout = 22 Ohms) and fed to an ADC.
36 compatible = "voltage-divider";
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| /Documentation/devicetree/bindings/clock/ti/ |
| D | divider.txt | 1 Binding for TI divider clock
6 register-mapped adjustable clock rate divider that does not gate and has
44 The binding must also provide the register to control the divider and
45 unless the divider array is provided, min and max dividers. Optionally
56 - compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
59 - reg : offset for register controlling adjustable divider
64 - ti,bit-shift : number of bits to shift the divider value, defaults to 0
78 - ti,latch-bit : latch the divider value to HW, only needed if the register
79 access requires this. As an example dra76x DPLL_GMAC H14 divider implements
85 compatible = "ti,divider-clock";
[all …]
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| D | composite.txt | 11 an adjustable clock rate divider, this behaves exactly as [3]
22 [3] Documentation/devicetree/bindings/clock/ti/divider.txt
42 compatible = "ti,composite-divider-clock";
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| /Documentation/devicetree/bindings/clock/ |
| D | nspire-clock.txt | 5 "lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
6 "lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
14 - clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
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| D | xgene.txt | 37 reset and/or the divider. Either may be omitted, but at least
55 - divider-offset : Offset to the divider CSR register from the divider base.
57 - divider-width : Width of the divider register. Default is 0.
58 - divider-shift : Bit shift of the divider register. Default is 0.
107 divider-offset = <0x238>;
108 divider-width = <0x9>;
109 divider-shift = <0x0>;
125 divider-offset = <0x10>;
126 divider-width = <0x2>;
127 divider-shift = <0x0>;
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| D | keystone-pll.txt | 4 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
18 - reg-names : control, multiplier and post-divider. The multiplier and
19 post-divider registers are applicable only for main pll clock
20 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
29 reg-names = "control", "multiplier", "post-divider";
66 - compatible : shall be "ti,keystone,pll-divider-clock"
70 - bit-mask : arbitrary bitmask for programming the divider
78 compatible = "ti,keystone,pll-divider-clock";
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| D | dove-divider-clock.txt | 1 PLL divider based Dove clocks
17 - compatible : shall be "marvell,dove-divider-clock"
18 - reg : shall be the register address of the Core PLL and Clock Divider
20 Core PLL and Clock Divider Control 1 register. Thus, it will have
25 compatible = "marvell,dove-divider-clock";
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| D | altr_socfpga.txt | 21 - fixed-divider : If clocks have a fixed divider value, use this property.
25 the divider register, bit shift, and width.
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| D | silabs,si5351.txt | 43 - silabs,clock-source: source clock of the output divider stage N, shall be
50 divider.
89 * - multisynth0 as clock source of output divider
106 * - multisynth1 as clock source of output divider
119 * - xtal as clock source of output divider
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| D | mvebu-corediv-clock.txt | 1 * Core Divider Clock bindings for Marvell MVEBU SoCs
12 - reg : must be the register address of Core Divider control register
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| D | zx296718-clk.txt | 10 zx296718 top clock selection, divider and gating
17 zx296718 audio clock selection, divider and gating
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| /Documentation/devicetree/bindings/regulator/ |
| D | ltc3676.txt | 17 - lltc,fb-voltage-divider: An array of two integers containing the resistor
18 values R1 and R2 of the feedback voltage divider in ohms.
39 lltc,fb-voltage-divider = <127000 200000>;
48 lltc,fb-voltage-divider = <301000 200000>;
57 lltc,fb-voltage-divider = <127000 200000>;
66 lltc,fb-voltage-divider = <221000 200000>;
75 lltc,fb-voltage-divider = <487000 200000>;
89 lltc,fb-voltage-divider = <634000 200000>;
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| D | ltc3589.txt | 17 - lltc,fb-voltage-divider: An array of two integers containing the resistor
18 values R1 and R2 of the feedback voltage divider in ohms.
39 lltc,fb-voltage-divider = <100000 158000>;
48 lltc,fb-voltage-divider = <180000 191000>;
57 lltc,fb-voltage-divider = <270000 100000>;
66 lltc,fb-voltage-divider = <511000 158000>;
74 lltc,fb-voltage-divider = <100000 158000>;
82 lltc,fb-voltage-divider = <180000 191000>;
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| D | mps,mp886x.yaml | 28 mps,fb-voltage-divider:
30 values R1 and R2 of the feedback voltage divider in kilo ohms.
42 - mps,fb-voltage-divider
58 mps,fb-voltage-divider = <80 240>;
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| /Documentation/devicetree/bindings/spi/ |
| D | spi_oc_tiny.txt | 8 - baud-width: width, in bits, of the programmable divider used to scale
11 The clock-frequency and baud-width properties are needed only if the divider
12 is programmable. They are not needed if the divider is fixed.
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| /Documentation/devicetree/bindings/iio/frequency/ |
| D | adf4350.txt | 21 - adi,reference-div2-enable: Enables reference divider.
36 4: N-Divider output
48 - adi,12bit-clk-divider: Clock divider value used when
50 - adi,clk-divider-mode:
52 0: Clock divider off (default)
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| /Documentation/devicetree/bindings/hwmon/ |
| D | maxim,max20730.yaml | 36 vout-voltage-divider:
38 If voltage divider present at vout, the voltage at voltage sensor pin
40 meaningful number if voltage divider present. It has two numbers,
63 vout-voltage-divider = <1000 2000>; // vout would be scaled to 0.5
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| D | adi,adm1177.yaml | 42 Specifies which internal voltage divider to be used. A 1 selects
43 a 7:2 voltage divider while a 0 selects a 14:1 voltage divider.
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| /Documentation/devicetree/bindings/net/can/ |
| D | mpc5xxx-mscan.txt | 21 also specify which clock source and divider shall be used for the controller:
32 - fsl,mscan-clock-divider: for the reference and system clock, an additional
33 clock divider can be specified. By default, a
52 fsl,mscan-clock-divider = <3>;
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| /Documentation/hwmon/ |
| D | adm9240.rst | 96 clock via a divider to an 8-bit counter. Fan speed (rpm) is calculated by:
98 rpm = (22500 * 60) / (count * divider)
100 Automatic fan clock divider
105 - fan clock divider not changed
111 - fan clock divider set to max
121 - fan clock divider set to suit fan_min
130 * fan speed may be displayed as zero until the auto fan clock divider
131 adjuster brings fan speed clock divider back into chip measurement
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| D | ltc4260.rst | 44 registers. If a set of voltage divider resistors is installed, calculate the
46 value of the divider resistor against the measured voltage and R2 is the value
47 of the divider resistor against Ground.
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| D | ltc4261.rst | 44 registers. If a set of voltage divider resistors is installed, calculate the
46 value of the divider resistor against the measured voltage and R2 is the value
47 of the divider resistor against Ground.
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| D | emc2103.rst | 25 readings can be divided by a programmable divider (1, 2, 4 or 8) to give
27 represented, so some rounding is done. With a divider of 1, the lowest
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| /Documentation/devicetree/bindings/mfd/ |
| D | gateworks-gsc.yaml | 68 (i.e. voltage rail with a pre-scaling resistor divider).
83 2 - scaled voltage based on an optional resistor divider
89 gw,voltage-divider-ohms:
90 description: Values of resistors for divider on raw ADC input
182 gw,voltage-divider-ohms = <22100 1000>;
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| /Documentation/devicetree/bindings/mmc/ |
| D | exynos-dw-mshc.txt | 26 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
28 ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7.
50 - when CIU clock divider value is set to 3, all possible 8 phase shift
52 - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
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