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/Documentation/devicetree/bindings/perf/
Darm,cmn.yaml30 description: One interrupt for each DTC domain implemented must
53 /* 4x2 mesh with one DTC, and CFG node at 0,1,1,0 */
/Documentation/admin-guide/perf/
Darm-cmn.rst13 global counters implemented by the main controller (DTC), which provides
34 * The cycle counter is treated as a synthetic event belonging to the DTC
/Documentation/devicetree/
Ddynamic-resolution-notes.rst14 proper dtc option and having a /plugin/ tag. This generates the
Dwriting-schema.rst94 dtc. They are simplified to make them more compact and avoid a bunch of
123 dtc must also be built with YAML output support enabled. This requires that
Dof_unittest.rst44 $(call if_changed_dep, dtc)
/Documentation/
Ddontdiff123 dtc
/Documentation/devicetree/bindings/pinctrl/
Dnvidia,tegra20-pinmux.txt76 ddc, dta, dtb, dtc, dtd, dte, dtf, gma, gmb, gmc, gmd, gme, gpu, gpu7,
/Documentation/devicetree/bindings/
Dexample-schema.yaml234 # Examples are now compiled with dtc and validated against the schemas
/Documentation/devicetree/bindings/iio/temperature/
Dadi,ltc2983.yaml120 Note should be signed, but dtc doesn't currently maintain the
/Documentation/kbuild/
Dmakefiles.rst1349 dtc