Searched full:efuse (Results 1 – 25 of 35) sorted by relevance
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| /Documentation/devicetree/bindings/nvmem/ |
| D | rockchip-efuse.yaml | 4 $id: http://devicetree.org/schemas/nvmem/rockchip-efuse.yaml#
7 title: Rockchip eFuse device tree bindings
18 - rockchip,rk3066a-efuse
19 - rockchip,rk3188-efuse
20 - rockchip,rk3228-efuse
21 - rockchip,rk3288-efuse
22 - rockchip,rk3328-efuse
23 - rockchip,rk3368-efuse
24 - rockchip,rk3399-efuse
27 - rockchip,rockchip-efuse
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| D | mtk-efuse.txt | 1 = Mediatek MTK-EFUSE device tree bindings =
3 This binding is intended to represent MTK-EFUSE which is found in most Mediatek SOCs.
7 "mediatek,mt7622-efuse", "mediatek,efuse": for MT7622
8 "mediatek,mt7623-efuse", "mediatek,efuse": for MT7623
9 "mediatek,mt8173-efuse" or "mediatek,efuse": for MT8173
13 Are child nodes of MTK-EFUSE, bindings of which as described in
18 efuse: efuse@10206000 {
19 compatible = "mediatek,mt8173-efuse";
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| D | amlogic-meson-mx-efuse.txt | 1 Amlogic Meson6/Meson8/Meson8b efuse
5 - "amlogic,meson6-efuse"
6 - "amlogic,meson8-efuse"
7 - "amlogic,meson8b-efuse"
8 - reg: base address and size of the efuse registers
9 - clocks: a reference to the efuse core gate clock
17 efuse: nvmem@0 {
18 compatible = "amlogic,meson8-efuse";
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| D | sc27xx-efuse.txt | 1 = Spreadtrum SC27XX PMIC eFuse device tree bindings =
5 "sprd,sc2720-efuse"
6 "sprd,sc2721-efuse"
7 "sprd,sc2723-efuse"
8 "sprd,sc2730-efuse"
9 "sprd,sc2731-efuse"
10 - reg: Specify the address offset of efuse controller.
14 Are child nodes of eFuse, bindings of which as described in
29 efuse@380 {
30 compatible = "sprd,sc2731-efuse";
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| D | uniphier-efuse.txt | 1 = UniPhier eFuse device tree bindings =
3 This UniPhier eFuse must be under soc-glue.
6 - compatible: should be "socionext,uniphier-efuse"
10 Are child nodes of efuse, bindings of which as described in
22 efuse@100 {
23 compatible = "socionext,uniphier-efuse";
27 efuse@200 {
28 compatible = "socionext,uniphier-efuse";
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| D | amlogic-efuse.txt | 1 = Amlogic Meson GX eFuse device tree bindings =
4 - compatible: should be "amlogic,meson-gxbb-efuse"
5 - clocks: phandle to the efuse peripheral clock provided by the
10 Are child nodes of eFuse, bindings of which as described in
15 efuse: efuse {
16 compatible = "amlogic,meson-gxbb-efuse";
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| D | ingenic,jz4780-efuse.yaml | 4 $id: http://devicetree.org/schemas/nvmem/ingenic,jz4780-efuse.yaml#
7 title: Ingenic JZ EFUSE driver bindings
18 - ingenic,jz4780-efuse
24 # Handle for the ahb for the efuse.
38 efuse@134100d0 {
39 compatible = "ingenic,jz4780-efuse";
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| D | sprd-efuse.txt | 1 = Spreadtrum eFuse device tree bindings =
4 - compatible: Should be "sprd,ums312-efuse".
5 - reg: Specify the address offset of efuse controller.
11 Are child nodes of eFuse, bindings of which as described in
16 ap_efuse: efuse@32240000 {
17 compatible = "sprd,ums312-efuse";
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| D | qcom,qfprom.yaml | 7 title: Qualcomm Technologies Inc, QFPROM Efuse bindings
62 efuse@784000 {
87 efuse@784000 {
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| D | allwinner,sun4i-a10-sid.yaml | 41 efuse@1c23800 {
47 efuse@1c23800 {
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| D | imx-ocotp.yaml | 13 This binding represents the on-chip eFuse OTP controller found on
85 ocotp: efuse@21bc000 {
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| D | mxs-ocotp.yaml | 44 ocotp: efuse@8002c000 {
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| D | imx-iim.yaml | 50 iim: efuse@63f98000 {
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| D | st,stm32-romem.yaml | 49 efuse@1fff7800 {
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| /Documentation/devicetree/bindings/fuse/ |
| D | nvidia,tegra20-fuse.txt | 4 - compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30,
5 must contain "nvidia,tegra30-efuse". For Tegra114, must contain
6 "nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse".
7 For Tegra132 must contain "nvidia,tegra132-efuse", "nvidia,tegra124-efuse".
8 For Tegra210 must contain "nvidia,tegra210-efuse". For Tegra186 must contain
9 "nvidia,tegra186-efuse". For Tegra194 must contain "nvidia,tegra194-efuse".
10 For Tegra234 must contain "nvidia,tegra234-efuse".
12 nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
15 nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse:
16 The differences between these SoCs are the size of the efuse array,
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| /Documentation/devicetree/bindings/regulator/ |
| D | ti-abb-regulator.txt | 35 efuse: (see Optional properties)
36 RBB enable efuse Mask: (See Optional properties)
37 FBB enable efuse Mask: (See Optional properties)
38 Vset value efuse Mask: (See Optional properties)
47 - "efuse-address" - Contains efuse base address used to pick up ABB info.
49 "efuse-address" is required for this.
55 efuse: Mandatory if 'efuse-address' register is defined. Provides offset
56 from efuse-address to pick up ABB characteristics. Set to 0 if
57 'efuse-address' is not defined.
58 RBB enable efuse Mask: Optional if 'efuse-address' register is defined.
[all …]
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| /Documentation/devicetree/bindings/opp/ |
| D | ti-omap5-opp-supply.txt | 3 OMAP5, DRA7, and AM57 family of SoCs have Class0 AVS eFuse registers which
26 "ti,omap5-opp-supply" - OMAP5+ optimized voltages in efuse(class0)VDD
28 "ti,omap5-core-opp-supply" - OMAP5+ optimized voltages in efuse(class0) VDD
30 - reg: Address and length of the efuse register set for the device (mandatory
32 - ti,efuse-settings: An array of u32 tuple items providing information about
33 optimized efuse configuration. Each item consists of the following:
35 efuse_offseet: efuse offset from reg where the optimized voltage is stored.
56 ti,efuse-settings = <
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| D | allwinner,sun50i-h6-operating-points.yaml | 17 on the speedbin blown in the efuse combination. The
18 sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to
27 A phandle pointing to a nvmem-cells node representing the efuse
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| /Documentation/devicetree/bindings/edac/ |
| D | apm-xgene-edac.txt | 18 - regmap-efuse : Regmap of the PMD efuse resource.
66 efuse: efuse@1054a000 {
67 compatible = "apm,xgene-efuse", "syscon";
84 regmap-efuse = <&efuse>;
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| /Documentation/devicetree/bindings/phy/ |
| D | phy-mtk-xsphy.txt | 49 - mediatek,efuse-intr : u32, the selection of Internal Resistor
52 - mediatek,efuse-intr : u32, the selection of Internal Resistor
53 - mediatek,efuse-tx-imp : u32, the selection of TX Impedance
54 - mediatek,efuse-rx-imp : u32, the selection of RX Impedance
106 mediatek,efuse-intr = <28>;
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| /Documentation/ABI/testing/ |
| D | sysfs-driver-jz4780-efuse | 4 Description: read-only access to the efuse on the Ingenic JZ4780 SoC
5 The SoC has a one time programmable 8K efuse that is
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| /Documentation/devicetree/bindings/net/ |
| D | keystone-netcp.txt | 57 - Efuse MAC address register
149 - efuse-mac: If this is 1, then the MAC address for the interface is
150 obtained from the device efuse mac address register.
154 when it obtains the mac address from efuse.
159 ethernet.txt and only if efuse-mac is set to 0. If all of the optional MAC
167 reg-names = "efuse";
238 efuse-mac = <1>;
250 efuse-mac = <0>;
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| D | ti,k3-am654-cpsw-nuss.yaml | 126 ti,syscon-efuse:
130 to efuse IO range with MAC addresses
213 ti,syscon-efuse = <&mcu_conf 0x200>;
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| /Documentation/devicetree/bindings/cpufreq/ |
| D | ti-cpufreq.txt | 6 The ti-cpufreq driver can use revision and an efuse value from the SoC to
31 2. Which eFuse bits indicate this OPP is available
59 * 0x2 and 0x4 have eFuse bits that indicate if they are available or not
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| /Documentation/devicetree/bindings/clock/ |
| D | prima2-clock.txt | 37 efuse 22
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