Searched +full:exit +full:- +full:latency +full:- +full:us (Results 1 – 16 of 16) sorted by relevance
| /Documentation/devicetree/bindings/power/ |
| D | domain-idle-state.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/domain-idle-state.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
18 const: domain-idle-states
21 "^(cpu|cluster|domain)-":
28 const: domain-idle-state
30 entry-latency-us:
32 The worst case latency in microseconds required to enter the idle
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| D | power-domain.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/power-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rafael J. Wysocki <rjw@rjwysocki.net>
11 - Kevin Hilman <khilman@kernel.org>
12 - Ulf Hansson <ulf.hansson@linaro.org>
24 \#power-domain-cells property in the PM domain provider node.
28 pattern: "^(power-controller|power-domain)([@-].*)?$"
30 domain-idle-states:
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| /Documentation/devicetree/bindings/arm/ |
| D | idle-states.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
14 1 - Introduction
18 where cores can be put in different low-power states (ranging from simple wfi
20 range of dynamic idle states that a processor can enter at run-time, can be
22 enter/exit specific idle states on a given processor.
27 - Running
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| D | psci.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
15 processors") can be used by Linux to initiate various CPU-centric power
25 r0 => 32-bit Function ID / return value
26 {r1 - r3} => Parameters
40 - description:
44 - description:
46 const: arm,psci-0.2
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| D | cpu-capacity.txt | 6 1 - Introduction
15 2 - CPU capacity definition
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
29 * A "single-threaded" or CPU affine benchmark
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
54 available, final capacities are calculated by directly using capacity-dmips-
58 4 - Examples
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| /Documentation/devicetree/bindings/thermal/ |
| D | thermal-idle.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/thermal/thermal-idle.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Daniel Lezcano <daniel.lezcano@linaro.org>
22 const: thermal-idle
24 A thermal-idle node describes the idle cooling device properties to
27 '#cooling-cells':
31 the cooling-maps reference. The first cell is the minimum cooling state
34 duration-us:
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| /Documentation/devicetree/bindings/arm/msm/ |
| D | qcom,idle-state.txt | 3 ARM provides idle-state node to define the cpuidle states, as defined in [1].
4 cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
5 states. Idle states have different enter/exit latency and residency values.
6 The idle states supported by the QCOM SoC are defined as -
31 state. Retention may have a slightly higher latency than Standby.
44 code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
50 be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
52 power modes possible at this state is vast, the exit latency and the residency
58 The idle-state for QCOM SoCs are distinguished by the compatible property of
59 the idle-states device node.
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| /Documentation/trace/ |
| D | ftrace.rst | 2 ftrace - Function Tracer
13 - Written for: 2.6.28-rc2
14 - Updated for: 3.10
15 - Updated for: 4.13 - Copyright 2017 VMware Inc. Steven Rostedt
16 - Converted to rst format - Changbin Du <changbin.du@intel.com>
19 ------------
24 performance issues that take place outside of user-space.
28 There's latency tracing to examine what occurs between interrupts
41 ----------------------
43 See :doc:`ftrace-design` for details for arch porters and such.
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| /Documentation/admin-guide/pm/ |
| D | intel_idle.rst | 1 .. SPDX-License-Identifier: GPL-2.0
28 processor's functional blocks into low-power states. That instruction takes two
38 only way to pass early-configuration-time parameters to it is via the kernel
42 .. _intel-idle-enumeration-of-states:
50 as C-states (in the ACPI terminology) or idle states. The list of meaningful
51 ``MWAIT`` hint values and idle states (i.e. low-power configurations of the
56 subsystem (see :ref:`idle-states-representation` in :doc:`cpuidle`),
65 `below <intel-idle-parameters_>`_.]
82 configured to ignore the ACPI tables; see `below <intel-idle-parameters_>`_.]
85 initialized to represent a "polling idle state" (a pseudo-idle state in which
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| /Documentation/driver-api/thermal/ |
| D | cpu-idle-cooling.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 ----------
26 budget lower than the requested one and under-utilize the CPU, thus
27 losing performance. In other words, one OPP under-utilizes the CPU
33 ----------
58 ---------------
70 performance penalty and a fixed latency. Mitigation can be increased
78 |------- -------
81 <------>
82 idle <---------------------->
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| /Documentation/accounting/ |
| D | psi.rst | 4 PSI - Pressure Stall Information
11 latency spikes, throughput losses, and run the risk of OOM kills.
14 either play it safe and under-utilize their hardware resources, or
23 scarcity aids users in sizing workloads to hardware--or provisioning
38 respective file in /proc/pressure/ -- cpu, memory, and io.
52 The "full" line indicates the share of time in which all non-idle
64 (in us) is tracked and exported as well, to allow detection of latency
84 <some|full> <stall amount in us> <time window in us>
99 psi metric and deactivates upon exit from the stall state. While system is
113 Notifications to the userspace are rate-limited to one per tracking window.
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| /Documentation/admin-guide/sysctl/ |
| D | net.rst | 9 - Terrehon Bowden <terrehon@pacbell.net>
10 - Bodo Bauer <bb@ricochet.net>
14 - Jorge Nerin <comandante@zaralinux.com>
18 - Shen Feng <shen@cn.fujitsu.com>
22 ------------------------------------------------------------------------------
47 1. /proc/sys/net/core - Network core options
51 --------------
63 - x86_64
64 - x86_32
65 - arm64
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| /Documentation/RCU/ |
| D | whatisRCU.rst | 3 What is RCU? -- "Read, Copy, Update"
21 during the 2.5 development effort that is optimized for read-mostly
40 :ref:`6. ANALOGY WITH READER-WRITER LOCKING <6_whatisRCU>`
58 everything, feel free to read the whole thing -- but if you are really
60 never need this document anyway. ;-)
65 ----------------
94 b. Wait for all previous readers to complete their RCU read-side
103 use much lighter-weight synchronization, in some cases, absolutely no
104 synchronization at all. In contrast, in more conventional lock-based
105 schemes, readers must use heavy-weight synchronization in order to
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| /Documentation/networking/dsa/ |
| D | sja1105.rst | 10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
17 These are SPI-managed automotive switches, with all ports being gigabit
21 set-and-forget use, with minimal dynamic interaction at runtime. They
56 Also the configuration is write-only (software cannot read it back from the
71 programmable filters for link-local destination MACs.
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| /Documentation/RCU/Design/Requirements/ |
| D | Requirements.rst | 16 ------------
18 Read-copy update (RCU) is a synchronization mechanism that is often used
19 as a replacement for reader-writer locking. RCU is unusual in that
20 updaters do not block readers, which means that RCU's read-side
28 thought of as an informal, high-level specification for RCU. It is
40 #. `Fundamental Non-Requirements`_
42 #. `Quality-of-Implementation Requirements`_
44 #. `Software-Engineering Requirements`_
53 ------------------------
58 #. `Grace-Period Guarantee`_
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| /Documentation/RCU/Design/Data-Structures/ |
| D | Data-Structures.rst | 15 Data-Structure Relationships
25 .. kernel-figure:: BigTreeClassicRCU.svg
34 which results in a three-level ``rcu_node`` tree.
38 The purpose of this combining tree is to allow per-CPU events
39 such as quiescent states, dyntick-idle transitions,
42 Quiescent states are recorded by the per-CPU ``rcu_data`` structures,
43 and other events are recorded by the leaf-level ``rcu_node``
54 As can be seen from the diagram, on a 64-bit system
55 a two-level tree with 64 leaves can accommodate 1,024 CPUs, with a fanout
58 +-----------------------------------------------------------------------+
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