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/Documentation/hwmon/
Dmc13783-adc.rst33 Some channels can be used as General Purpose inputs or in a dedicated mode with
37 the General Purpose inputs and touchscreen.
53 5 General Purpose ADIN5 / Battery Pack Thermistor 0 - 2.30V No
54 6 General Purpose ADIN6 / Backup Voltage (LICELL) 0 - 2.30V / No /
56 7 General Purpose ADIN7 / UID / Die Temperature 0 - 2.30V / No /
58 8 General Purpose ADIN8 0 - 2.30V No
59 9 General Purpose ADIN9 0 - 2.30V No
60 10 General Purpose ADIN10 0 - 2.30V No
61 11 General Purpose ADIN11 0 - 2.30V No
62 12 General Purpose TSX1 / Touchscreen X-plate 1 0 - 2.30V No
[all …]
/Documentation/devicetree/bindings/input/touchscreen/
Dbu21013.txt13 - touchscreen-size-x : General touchscreen binding, see [1].
14 - touchscreen-size-y : General touchscreen binding, see [1].
15 - touchscreen-inverted-x : General touchscreen binding, see [1].
16 - touchscreen-inverted-y : General touchscreen binding, see [1].
17 - touchscreen-swapped-x-y : General touchscreen binding, see [1].
19 [1] All general touchscreen properties are described in
Dads7846.txt62 touchscreen-size-x General touchscreen binding, see [1].
63 touchscreen-size-y General touchscreen binding, see [1].
64 touchscreen-max-pressure General touchscreen binding, see [1].
65 touchscreen-min-pressure General touchscreen binding, see [1].
66 touchscreen-average-samples General touchscreen binding, see [1].
67 touchscreen-inverted-x General touchscreen binding, see [1].
68 touchscreen-inverted-y General touchscreen binding, see [1].
69 touchscreen-swapped-x-y General touchscreen binding, see [1].
71 [1] All general touchscreen properties are described in
/Documentation/virt/kvm/
Ds390-diag.rst15 General remarks
44 General register 1 contains the virtio subfunction code. Supported
48 Upon completion of the DIAGNOSE instruction, general register 2 contains
64 General register 2 contains a subchannel-identification word denoting
67 General register 3 contains the number of the virtqueue to be notified.
69 General register 4 contains a 64bit identifier for KVM usage (the
70 kvm_io_bus cookie). If general register 4 does not contain a valid
73 After completion of the DIAGNOSE call, general register 2 may contain
/Documentation/devicetree/bindings/soc/rockchip/
Dgrf.txt1 * Rockchip General Register Files (GRF)
3 The general register file will be used to do static set by software, which
7 - GRF, used for general non-secure system,
8 - SGRF, used for general secure system,
14 - GRF, used for general non-secure system,
15 - SGRF, used for general secure system,
/Documentation/devicetree/bindings/clock/
Dpistachio-clock.txt5 general control, and top general control) which are instantiated individually
31 top-level general control.
71 Peripheral general control:
74 The peripheral general control block generates system interface clocks and
81 - reg: Must contain the base address and length of the peripheral general
99 Top-level general control:
102 The top-level general control block contains miscellaneous control registers and
/Documentation/devicetree/bindings/gpio/
Drockchip,rk3328-grf-gpio.txt1 Rockchip RK3328 GRF (General Register Files) GPIO controller.
4 control, can also be used for general purpose. It is manipulated by the
31 Note: The grf_gpio node should be declared as the child of the GRF (General
/Documentation/scsi/
DLICENSE.FlashPoint10 a) the GNU General Public License as published by the Free Software
19 or FITNESS FOR A PARTICULAR PURPOSE. See either the GNU General Public
22 You should have received a copy of the GNU General Public License along
39 This file is available under both the GNU General Public License
/Documentation/devicetree/bindings/mips/ingenic/
Ddevices.yaml41 - description: YSH & ATIL General Board, CU1000 Module with Neo Backplane
46 - description: YSH & ATIL General Board, CU1830 Module with Neo Backplane
51 - description: YSH & ATIL General Board, CU2000 Module with Neo Backplane
/Documentation/devicetree/bindings/mfd/
Dfsl-imx25-tsadc.txt3 This device combines two general purpose conversion queues one used for general
21 The first queue is for the touchscreen, the second for general purpose ADC.
/Documentation/devicetree/bindings/timer/
Dqcom,msm-timer.txt11 - interrupts : Interrupts for the debug timer, the first general purpose
12 timer, and optionally a second general purpose timer, and
23 - clock-frequency : The frequency of the debug timer and the general purpose
Dti,keystone-timer.txt4 architecture devices. The timer can be configured as a general-purpose 64-bit
5 timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
Dti,davinci-timer.txt4 architecture devices. The timer can be configured as a general-purpose 64-bit
5 timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
/Documentation/networking/device_drivers/atm/
Dcxacru-cf.py5 # under the terms of the GNU General Public License as published by the Free
11 # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 # You should have received a copy of the GNU General Public License along with
/Documentation/networking/
Dstrparser.rst17 The strparser works in one of two modes: receive callback or general
24 In general mode, a sequence of skbs are fed to strparser from an
49 callback mode; in general mode this is set to NULL. Callbacks
88 strp_process is called in general mode for a stream parser to
157 function is to lock_sock for the associated socket. In general
166 function is release_sock for the associated socket. In general
222 associated TCP socket. In general mode, the timeout is passed as an
234 In general mode the message length limit is passed in as an argument
/Documentation/userspace-api/media/
Dindex.rst58 GNU General Public License::
61 under the terms of the GNU General Public License as published by the Free
67 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
/Documentation/ABI/stable/
Dsysfs-driver-firmware-zynqmp6 Read/Write PMU global general storage register value,
8 Global general storage register that can be used
32 Read/Write PMU persistent global general storage register
34 Persistent global general storage register that
/Documentation/devicetree/bindings/sound/
Dtlv320adcx140.yaml88 Defines the configuration for the general purpose input pins (GPI).
92 1 - GPIX is configured as a general-purpose input (GPI)
121 Defines the configuration and output driver for the general purpose
129 1 - GPOX is configured as a general-purpose output (GPO)
145 Defines the configuration and output drive for the General Purpose
152 1 - GPIO1 is configured as a general-purpose output (GPO)
158 9 - GPIO1 is configured as a general-purpose input (GPI)
/Documentation/admin-guide/cifs/
Dwinucase_convert.pl9 # it under the terms of the GNU General Public License as published by
16 # GNU General Public License for more details.
18 # You should have received a copy of the GNU General Public License
/Documentation/security/
Dlsm.rst2 Linux Security Modules: General Security Hooks for Linux
30 general framework that would provide a set of security hooks to control
49 The LSM framework provides a general kernel framework to support
104 general security module stacking. It defines
129 The capabilities security module does not use the general security
/Documentation/userspace-api/media/drivers/
Dindex.rst14 under the terms of the GNU General Public License as published by the Free
19 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
/Documentation/devicetree/bindings/pinctrl/
Dcnxt,cx92755-pinctrl.txt1 Conexant Digicolor CX92755 General Purpose Pin Mapping
12 - reg: Base address of the General Purpose Pin Mapping register block and the
32 For a general description of GPIO bindings, please refer to ../gpio/gpio.txt.
/Documentation/nvdimm/
Dmaintainer-entry-profile.rst15 In general patches can be submitted against the latest -rc; however, if
40 Specification Working Group. In general, the stance of the subsystem is
57 In general, please wait up to one week before pinging for feedback. A
/Documentation/devicetree/bindings/mips/
Dmscc.txt15 functionalities: chip ID, general purpose register for software use, reset
32 the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
/Documentation/driver-api/media/
Dindex.rst46 under the terms of the GNU General Public License as published by the Free
52 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for

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