Searched +full:gpio +full:- +full:ranges (Results 1 – 25 of 118) sorted by relevance
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| /Documentation/devicetree/bindings/gpio/ |
| D | socionext,uniphier-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier GPIO controller
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
14 pattern: "^gpio@[0-9a-f]+$"
17 const: socionext,uniphier-gpio
22 gpio-controller: true
24 "#gpio-cells":
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| D | gpio.txt | 1 Specifying GPIO information for devices
5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
14 GPIO properties can contain one or more GPIO phandles, but only in exceptional
23 The following example could be used to describe GPIO pins used as device enable
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
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| D | abilis,tb10x-gpio.txt | 1 * Abilis TB10x GPIO controller
4 - compatible: Should be "abilis,tb10x-gpio"
5 - reg: Address and length of the register set for the device
6 - gpio-controller: Marks the device node as a gpio controller.
7 - #gpio-cells: Should be <2>. The first cell is the pin number and the
9 - bit 0 specifies polarity (0 for normal, 1 for inverted).
10 - abilis,ngpio: the number of GPIO pins this driver controls.
13 - interrupt-controller: Marks the device node as an interrupt controller.
14 - #interrupt-cells: Should be <1>. Interrupts are triggered on both edges.
15 - interrupts: Defines the interrupt line connecting this GPIO controller to
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| D | renesas,rcar-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/renesas,rcar-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car General-Purpose Input/Output Ports (GPIO)
10 - Geert Uytterhoeven <geert+renesas@glider.be>
15 - items:
16 - enum:
17 - renesas,gpio-r8a7778 # R-Car M1
18 - renesas,gpio-r8a7779 # R-Car H1
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| D | renesas,em-gio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/renesas,em-gio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Magnus Damm <magnus.damm@gmail.com>
14 const: renesas,em-gio
18 - description: First set of contiguous registers
19 - description: Second set of contiguous registers
23 - description: Interrupt for the first set of 16 GPIO ports
24 - description: Interrupt for the second set of 16 GPIO ports
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| D | zx296702-gpio.txt | 1 ZTE ZX296702 GPIO controller
4 - compatible : "zte,zx296702-gpio"
5 - #gpio-cells : Should be two. The first cell is the pin number and the
7 - bit 0 specifies polarity (0 for normal, 1 for inverted)
8 - gpio-controller : Marks the device node as a GPIO controller.
9 - interrupts : Interrupt mapping for GPIO IRQ.
10 - gpio-ranges : Interaction with the PINCTRL subsystem.
12 gpio1: gpio@b008040 {
13 compatible = "zte,zx296702-gpio";
15 gpio-controller;
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| D | gpio-atlas7.txt | 1 CSR SiRFatlas7 GPIO controller bindings
4 - compatible : "sirf,atlas7-gpio"
5 - reg : Address range of the pinctrl registers
6 - interrupts : Interrupts used by every GPIO group
7 - gpio-banks : How many gpio banks on this controller
8 - gpio-controller : Indicates this device is a GPIO controller
9 - interrupt-controller : Marks the device node as an interrupt controller
11 The GPIO controller also acts as an interrupt controller. It uses the default
13 interrupt-controller/interrupts.txt.
18 compatible = "sirf,atlas7-gpio";
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| D | gpio_oxnas.txt | 1 * Oxford Semiconductor OXNAS SoC GPIO Controller
3 Please refer to gpio.txt for generic information regarding GPIO bindings.
6 - compatible: "oxsemi,ox810se-gpio" or "oxsemi,ox820-gpio"
7 - reg: Base address and length for the device.
8 - interrupts: The port interrupt shared by all pins.
9 - gpio-controller: Marks the port as GPIO controller.
10 - #gpio-cells: Two. The first cell is the pin number and
11 the second cell is used to specify the gpio polarity as defined in
12 defined in <dt-bindings/gpio/gpio.h>:
15 - interrupt-controller: Marks the device node as an interrupt controller.
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| D | mrvl-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/gpio/mrvl-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell PXA GPIO controller
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Bartosz Golaszewski <bgolaszewski@baylibre.com>
12 - Rob Herring <robh+dt@kernel.org>
15 - if:
20 - intel,pxa25x-gpio
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| D | microchip,pic32-gpio.txt | 1 * Microchip PIC32 GPIO devices (PIO).
4 - compatible: "microchip,pic32mzda-gpio"
5 - reg: Base address and length for the device.
6 - interrupts: The port interrupt shared by all pins.
7 - gpio-controller: Marks the port as GPIO controller.
8 - #gpio-cells: Two. The first cell is the pin number and
9 the second cell is used to specify the gpio polarity as defined in
10 defined in <dt-bindings/gpio/gpio.h>:
14 - interrupt-controller: Marks the device node as an interrupt controller.
15 - #interrupt-cells: Two. The first cell is the GPIO number and second cell
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| D | gpio-vf610.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-vf610.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale VF610 PORT/GPIO module
10 - Stefan Agner <stefan@agner.ch>
13 The Freescale PORT/GPIO modules are two adjacent modules providing GPIO
17 Note: Each GPIO port should have an alias correctly numbered in "aliases"
23 - const: fsl,vf610-gpio
24 - items:
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| /Documentation/devicetree/bindings/mfd/ |
| D | st,stmfx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectonics Multi-Function eXpander (STMFX) bindings
9 description: ST Multi-Function eXpander (STMFX) is a slave controller using I2C for
10 communication with the main MCU. Its main features are GPIO expansion,
15 - Amelie Delaunay <amelie.delaunay@st.com>
19 const: st,stmfx-0300
27 drive-open-drain: true
29 vdd-supply:
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | st,stm32-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: STM32 GPIO and Pin Mux/Config controller
11 - Alexandre TORGUE <alexandre.torgue@st.com>
14 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
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| D | abilis,tb10x-iomux.txt | 5 -------------------
7 - compatible: should be "abilis,tb10x-iomux";
8 - reg: should contain the physical address and size of the pin controller's
13 --------------------
15 Functions are defined (and referenced) by sub-nodes of the pin controller.
16 Every sub-node defines exactly one function (implying a set of pins).
19 controller sub-nodes.
22 - abilis,function: should be set to the name of the function's pin group.
25 - GPIO ports: gpioa, gpiob, gpioc, gpiod, gpioe, gpiof, gpiog,
27 - Serial TS input ports: mis0, mis1, mis2, mis3, mis4, mis5, mis6, mis7
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| D | qcom,msm8226-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,msm8226-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
18 const: qcom,msm8226-pinctrl
28 interrupt-controller: true
30 '#interrupt-cells':
32 include/dt-bindings/interrupt-controller/irq.h
35 gpio-controller: true
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| D | renesas,rza2-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza2-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/A2 combined Pin and GPIO controller
10 - Chris Brandt <chris.brandt@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
14 The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
17 Each port features up to 8 pins, each of them configurable for GPIO function
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| D | mscc,ocelot-pinctrl.txt | 2 ----------------------------------------------------
5 - compatible : Should be "mscc,ocelot-pinctrl",
6 "mscc,jaguar2-pinctrl" or "microchip,sparx5-pinctrl"
7 - reg : Address and length of the register set for the device
8 - gpio-controller : Indicates this device is a GPIO controller
9 - #gpio-cells : Must be 2.
11 second cell specifies GPIO flags, as defined in
12 <dt-bindings/gpio/gpio.h>.
13 - gpio-ranges : Range of pins managed by the GPIO controller.
16 The ocelot-pinctrl driver uses the generic pin multiplexing and generic pin
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| D | qcom,ipq8064-pinctrl.txt | 4 - compatible: "qcom,ipq8064-pinctrl"
5 - reg: Should be the base address and length of the TLMM block.
6 - interrupts: Should be the parent IRQ of the TLMM block.
7 - interrupt-controller: Marks the device node as an interrupt controller.
8 - #interrupt-cells: Should be two.
9 - gpio-controller: Marks the device node as a GPIO controller.
10 - #gpio-cells : Should be two.
11 The first cell is the gpio pin number and the
13 - gpio-ranges: see ../gpio/gpio.txt
17 - gpio-reserved-ranges: see ../gpio/gpio.txt
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| D | qcom,msm8660-pinctrl.txt | 4 - compatible: "qcom,msm8660-pinctrl"
5 - reg: Should be the base address and length of the TLMM block.
6 - interrupts: Should be the parent IRQ of the TLMM block.
7 - interrupt-controller: Marks the device node as an interrupt controller.
8 - #interrupt-cells: Should be two.
9 - gpio-controller: Marks the device node as a GPIO controller.
10 - #gpio-cells : Should be two.
11 The first cell is the gpio pin number and the
13 - gpio-ranges: see ../gpio/gpio.txt
17 - gpio-reserved-ranges: see ../gpio/gpio.txt
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| D | qcom,apq8064-pinctrl.txt | 4 - compatible: "qcom,apq8064-pinctrl"
5 - reg: Should be the base address and length of the TLMM block.
6 - interrupts: Should be the parent IRQ of the TLMM block.
7 - interrupt-controller: Marks the device node as an interrupt controller.
8 - #interrupt-cells: Should be two.
9 - gpio-controller: Marks the device node as a GPIO controller.
10 - #gpio-cells : Should be two.
11 The first cell is the gpio pin number and the
13 - gpio-ranges: see ../gpio/gpio.txt
17 - gpio-reserved-ranges: see ../gpio/gpio.txt
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| D | qcom,ipq4019-pinctrl.txt | 7 - compatible: "qcom,ipq4019-pinctrl"
8 - reg: Should be the base address and length of the TLMM block.
9 - interrupts: Should be the parent IRQ of the TLMM block.
10 - interrupt-controller: Marks the device node as an interrupt controller.
11 - #interrupt-cells: Should be two.
12 - gpio-controller: Marks the device node as a GPIO controller.
13 - #gpio-cells : Should be two.
14 The first cell is the gpio pin number and the
16 - gpio-ranges: see ../gpio/gpio.txt
20 - gpio-reserved-ranges: see ../gpio/gpio.txt
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| D | fsl,imx27-pinctrl.txt | 4 - compatible: "fsl,imx27-iomuxc"
9 - fsl,pins: three integers array, represents a group of pins mux and config
21 0 - Primary function
22 1 - Alternate function
23 2 - GPIO
24 Registers: GIUS (GPIO In Use), GPR (General Purpose Register)
28 0 - Input
29 1 - Output
32 gpio_oconf configures the gpio submodule output signal. This does not
33 have any effect unless GPIO function is selected. A/B/C_IN are output
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| D | marvell,armada-37xx-pinctrl.txt | 1 * Marvell Armada 37xx SoC pin and gpio controller
3 Each Armada 37xx SoC come with two pin and gpio controller one for the
6 Inside this set of register the gpio latch allows exposing some
11 GPIO and pin controller:
12 ------------------------
16 Refer to pinctrl-bindings.txt in this directory for details of the
22 - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
24 "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
26 - reg: The first set of register are for pinctrl/gpio and the second
28 - interrupts: list of the interrupt use by the gpio
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-pxa-pci-ce4100.txt | 2 ----------
4 CE4100 has one PCI device which is described as the I2C-Controller. This
5 PCI device has three PCI-bars, each bar contains a complete I2C
6 controller. So we have a total of three independent I2C-Controllers
8 The driver is probed via the PCI-ID and is gathering the information of
10 Grant Likely recommended to use the ranges property to map the PCI-Bar
15 ranges describes how the parent pci address space
22 non-zero if you had 2 or more devices mapped off
25 ranges allows the address mapping to be described
30 ------------------------------------------------
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| /Documentation/devicetree/bindings/mmc/ |
| D | mmc-spi-slot.txt | 7 - spi-max-frequency : maximum frequency for this device (Hz).
8 - voltage-ranges : two cells are required, first cell specifies minimum
10 Several ranges could be specified.
13 - gpios : may specify GPIOs in this order: Card-Detect GPIO,
14 Write-Protect GPIO. Note that this does not follow the
19 mmc-slot@0 {
20 compatible = "fsl,mpc8323rdb-mmc-slot",
21 "mmc-spi-slot";
25 voltage-ranges = <3300 3300>;
26 spi-max-frequency = <50000000>;
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