| /Documentation/translations/zh_CN/ |
| D | gpio.txt | 1 Chinese translated version of Documentation/admin-guide/gpio
13 Documentation/admin-guide/gpio 的中文翻译
27 GPIO 接口
37 "通用输入/输出口"(GPIO)是一个灵活的由软件控制的数字信号。他们可
40 “球珠”的一个位。电路板原理图显示了 GPIO 与外部硬件的连接关系。
43 片上系统 (SOC) 处理器对 GPIO 有很大的依赖。在某些情况下,每个
44 非专用引脚都可配置为 GPIO,且大多数芯片都最少有一些 GPIO。
45 可编程逻辑器件(类似 FPGA) 可以方便地提供 GPIO。像电源管理和
48 芯片。大多数 PC 的南桥有一些拥有 GPIO 能力的引脚 (只有BIOS
51 GPIO 的实际功能因系统而异。通常用法有:
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | marvell,armada-375-pinctrl.txt | 16 mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1)
17 mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi)
18 mpp2 2 gpio, dev(ad4), ptp(evreq), led(c0), audio(sdi)
19 mpp3 3 gpio, dev(ad5), ptp(trig), led(p3), audio(mclk)
20 mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso)
21 mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2)
22 mpp6 6 gpio, dev(ad0), led(p1), audio(lrclk)
23 mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk)
24 mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0)
25 mpp9 9 gpio, spi0(sck), spi1(sck), nand(we)
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| D | marvell,armada-37xx-pinctrl.txt | 1 * Marvell Armada 37xx SoC pin and gpio controller
3 Each Armada 37xx SoC come with two pin and gpio controller one for the
6 Inside this set of register the gpio latch allows exposing some
11 GPIO and pin controller:
26 - reg: The first set of register are for pinctrl/gpio and the second
28 - interrupts: list of the interrupt use by the gpio
34 - functions jtag, gpio
38 - functions sdio, gpio
42 - functions emmc, gpio
46 - functions pwm, led, gpio
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| D | marvell,armada-xp-pinctrl.txt | 21 mpp0 0 gpio, ge0(txclkout), lcd(d0)
22 mpp1 1 gpio, ge0(txd0), lcd(d1)
23 mpp2 2 gpio, ge0(txd1), lcd(d2)
24 mpp3 3 gpio, ge0(txd2), lcd(d3)
25 mpp4 4 gpio, ge0(txd3), lcd(d4)
26 mpp5 5 gpio, ge0(txctl), lcd(d5)
27 mpp6 6 gpio, ge0(rxd0), lcd(d6)
28 mpp7 7 gpio, ge0(rxd1), lcd(d7)
29 mpp8 8 gpio, ge0(rxd2), lcd(d8)
30 mpp9 9 gpio, ge0(rxd3), lcd(d9)
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| D | marvell,kirkwood-pinctrl.txt | 24 mpp0 0 gpio, nand(io2), spi(cs)
28 mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
32 mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
34 mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
37 mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
40 mpp13 13 gpio, sdio(cmd), uart1(txd)
41 mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col)
42 mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd)
43 mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
44 mpp17 17 gpio, sdio(d3)
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| D | marvell,orion-pinctrl.txt | 24 mpp0 0 pcie(rstout), pci(req2), gpio
25 mpp1 1 gpio, pci(gnt2)
26 mpp2 2 gpio, pci(req3), pci-1(pme)
27 mpp3 3 gpio, pci(gnt3)
28 mpp4 4 gpio, pci(req4)
29 mpp5 5 gpio, pci(gnt4)
30 mpp6 6 gpio, pci(req5), pci-1(clk)
31 mpp7 7 gpio, pci(gnt5), pci-1(clk)
32 mpp8 8 gpio, ge(col)
33 mpp9 9 gpio, ge(rxerr)
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| D | brcm,iproc-gpio.txt | 1 Broadcom iProc GPIO/PINCONF Controller
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
25 GPIO/PINCONF controller registers
28 Total number of in-use slots in GPIO controller
30 - #gpio-cells:
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| D | marvell,armada-39x-pinctrl.txt | 18 mpp0 0 gpio, ua0(rxd)
19 mpp1 1 gpio, ua0(txd)
20 mpp2 2 gpio, i2c0(sck)
21 mpp3 3 gpio, i2c0(sda)
22 mpp4 4 gpio, ua1(txd), ua0(rts), smi(mdc)
23 mpp5 5 gpio, ua1(rxd), ua0(cts), smi(mdio)
24 mpp6 6 gpio, dev(cs3), xsmi(mdio)
25 mpp7 7 gpio, dev(ad9), xsmi(mdc)
26 mpp8 8 gpio, dev(ad10), ptp(trig)
27 mpp9 9 gpio, dev(ad11), ptp(clk)
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| D | marvell,armada-38x-pinctrl.txt | 18 mpp0 0 gpio, ua0(rxd)
19 mpp1 1 gpio, ua0(txd)
20 mpp2 2 gpio, i2c0(sck)
21 mpp3 3 gpio, i2c0(sda)
22 mpp4 4 gpio, ge(mdc), ua1(txd), ua0(rts)
23 mpp5 5 gpio, ge(mdio), ua1(rxd), ua0(cts)
24 mpp6 6 gpio, ge0(txclkout), ge0(crs), dev(cs3)
25 mpp7 7 gpio, ge0(txd0), dev(ad9)
26 mpp8 8 gpio, ge0(txd1), dev(ad10)
27 mpp9 9 gpio, ge0(txd2), dev(ad11)
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| /Documentation/devicetree/bindings/gpio/ |
| D | fsl-imx-gpio.yaml | 4 $id: http://devicetree.org/schemas/gpio/fsl-imx-gpio.yaml#
7 title: Freescale i.MX/MXC GPIO controller
16 - fsl,imx1-gpio
17 - fsl,imx21-gpio
18 - fsl,imx31-gpio
19 - fsl,imx35-gpio
20 - fsl,imx7d-gpio
22 - const: fsl,imx35-gpio
23 - const: fsl,imx31-gpio
26 - fsl,imx50-gpio
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| D | renesas,rcar-gpio.yaml | 4 $id: http://devicetree.org/schemas/gpio/renesas,rcar-gpio.yaml#
7 title: Renesas R-Car General-Purpose Input/Output Ports (GPIO)
17 - renesas,gpio-r8a7778 # R-Car M1
18 - renesas,gpio-r8a7779 # R-Car H1
19 - const: renesas,rcar-gen1-gpio # R-Car Gen1
23 - renesas,gpio-r8a7742 # RZ/G1H
24 - renesas,gpio-r8a7743 # RZ/G1M
25 - renesas,gpio-r8a7744 # RZ/G1N
26 - renesas,gpio-r8a7745 # RZ/G1E
27 - renesas,gpio-r8a77470 # RZ/G1C
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| D | 8xxx_gpio.txt | 1 GPIO controllers on MPC8xxx SoCs
3 This is for the non-QE/CPM/GUTs GPIO controllers as found on
6 Every GPIO controller node must have #gpio-cells property defined,
7 this information will be used to translate gpio-specifiers.
8 See bindings/gpio/gpio.txt for details of how to specify GPIO
11 The GPIO module usually is connected to the SoC's internal interrupt
13 interrupt client nodes section) for details how to specify this GPIO
16 The GPIO module may serve as another interrupt controller (cascaded to
22 - compatible: "fsl,<chip>-gpio" followed by "fsl,mpc8349-gpio"
23 for 83xx, "fsl,mpc8572-gpio" for 85xx, or
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| D | nxp,lpc1850-gpio.txt | 1 NXP LPC18xx/43xx GPIO controller Device Tree Bindings
5 - compatible : Should be "nxp,lpc1850-gpio"
6 - reg : List of addresses and lengths of the GPIO controller
8 - reg-names : Should be "gpio", "gpio-pin-ic", "gpio-group0-ic" and
9 "gpio-gpoup1-ic"
10 - clocks : Phandle and clock specifier pair for GPIO controller
11 - resets : Phandle and reset specifier pair for GPIO controller
12 - gpio-controller : Marks the device node as a GPIO controller
13 - #gpio-cells : Should be two:
14 - The first cell is the GPIO line number
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| D | gpio-mxs.yaml | 4 $id: http://devicetree.org/schemas/gpio/gpio-mxs.yaml#
7 title: Freescale MXS GPIO controller
14 The Freescale MXS GPIO controller is part of MXS PIN controller.
16 As the GPIO controller is embedded in the PIN controller and all the
17 GPIO ports share the same IO space with PIN controller, the GPIO node
35 "gpio@[0-9]+$":
40 - fsl,imx23-gpio
41 - fsl,imx28-gpio
55 "#gpio-cells":
58 gpio-controller: true
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| D | gpio.txt | 1 Specifying GPIO information for devices
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
14 GPIO properties can contain one or more GPIO phandles, but only in exceptional
23 The following example could be used to describe GPIO pins used as device enable
27 gpio-controller;
28 #gpio-cells = <2>;
37 In the above example, &gpio1 uses 2 cells to specify a gpio. The first cell is
38 a local offset to the GPIO line and the second cell represent consumer flags,
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| D | mrvl-gpio.yaml | 4 $id: http://devicetree.org/schemas/gpio/mrvl-gpio.yaml#
7 title: Marvell PXA GPIO controller
20 - intel,pxa25x-gpio
21 - intel,pxa26x-gpio
22 - intel,pxa27x-gpio
23 - intel,pxa3xx-gpio
39 - marvell,mmp-gpio
40 - marvell,mmp2-gpio
51 pattern: '^gpio@[0-9a-f]+$'
55 - intel,pxa25x-gpio
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| D | gpio-davinci.txt | 1 Davinci/Keystone GPIO controller bindings
4 - compatible: should be "ti,dm6441-gpio": for Davinci da850 SoCs
5 "ti,keystone-gpio": for Keystone 2 66AK2H/K, 66AK2L,
7 "ti,k2g-gpio", "ti,keystone-gpio": for 66AK2G
8 "ti,am654-gpio", "ti,keystone-gpio": for TI K3 AM654
9 "ti,j721e-gpio", "ti,keystone-gpio": for J721E SoCs
14 - gpio-controller : Marks the device node as a gpio controller.
16 - #gpio-cells : Should be two.
20 - interrupts: Array of GPIO interrupt number. Only banked or unbanked IRQs are
23 - ti,ngpio: The number of GPIO pins supported.
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| D | nvidia,tegra186-gpio.txt | 1 NVIDIA Tegra186 GPIO controllers
3 Tegra186 contains two GPIO controllers; a main controller and an "AON"
9 The Tegra186 GPIO controller allows software to set the IO direction of, and
10 read/write the value of, numerous GPIO signals. Routing of GPIO signals to
14 a) Security registers, which allow configuration of allowed access to the GPIO
17 varies between the different GPIO controllers.
20 that wishes to configure access to the GPIO registers needs access to these
21 registers to do so. Code which simply wishes to read or write GPIO data does not
24 b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
27 documentation for rationale. Any particular GPIO client is expected to access
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| D | gpio_oxnas.txt | 1 * Oxford Semiconductor OXNAS SoC GPIO Controller
3 Please refer to gpio.txt for generic information regarding GPIO bindings.
6 - compatible: "oxsemi,ox810se-gpio" or "oxsemi,ox820-gpio"
9 - gpio-controller: Marks the port as GPIO controller.
10 - #gpio-cells: Two. The first cell is the pin number and
11 the second cell is used to specify the gpio polarity as defined in
12 defined in <dt-bindings/gpio/gpio.h>:
16 - #interrupt-cells: Two. The first cell is the GPIO number and second cell
22 - gpio-ranges: Interaction with the PINCTRL subsystem, it also specifies the
23 gpio base and count, should be in the format of numeric-gpio-range as
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| D | snps,creg-gpio.txt | 1 Synopsys GPIO via CREG (Control REGisters) driver
4 - compatible : "snps,creg-gpio-hsdk" or "snps,creg-gpio-axs10x".
6 - #gpio-cells : Since the generic GPIO binding is used, the
9 See "gpio-specifier" in .../devicetree/bindings/gpio/gpio.txt.
10 - gpio-controller : Marks the device node as a GPIO controller.
11 - ngpios: Number of GPIO pins.
15 gpio: gpio@f00014b0 {
16 compatible = "snps,creg-gpio-hsdk";
18 gpio-controller;
19 #gpio-cells = <2>;
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| D | intel,ixp4xx-gpio.txt | 1 Intel IXP4xx XScale Networking Processors GPIO
3 This GPIO controller is found in the Intel IXP4xx processors.
4 It supports 16 GPIO lines.
6 The interrupt portions of the GPIO controller is hierarchical:
7 the synchronous edge detector is part of the GPIO block, but the
10 the first 12 GPIO lines to 12 system interrupts.
12 The remaining 4 GPIO lines can not be used for receiving
15 The interrupt parent of this GPIO controller must be the
21 "intel,ixp4xx-gpio"
23 - gpio-controller : marks this as a GPIO controller
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| D | gpio-mpc8xxx.txt | 1 * Freescale MPC512x/MPC8xxx/QorIQ/Layerscape GPIO controller
4 - compatible : Should be "fsl,<soc>-gpio"
10 - #gpio-cells : Should be two. The first cell is the pin number and
11 the second cell is used to specify the gpio polarity:
16 - little-endian : GPIO registers are used as little endian. If not
19 Example of gpio-controller node for a mpc5125 SoC:
21 gpio0: gpio@1100 {
22 compatible = "fsl,mpc5125-gpio";
23 #gpio-cells = <2>;
28 Example of gpio-controller node for a ls2080a SoC:
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| /Documentation/driver-api/gpio/ |
| D | drivers-on-gpio.rst | 2 Subsystem drivers using GPIO
5 Note that standard kernel drivers exist for common GPIO tasks and will provide
10 - leds-gpio: drivers/leds/leds-gpio.c will handle LEDs connected to GPIO
13 - ledtrig-gpio: drivers/leds/trigger/ledtrig-gpio.c will provide a LED trigger,
14 i.e. a LED will turn on/off in response to a GPIO line going high or low
15 (and that LED may in turn use the leds-gpio as per above).
17 - gpio-keys: drivers/input/keyboard/gpio_keys.c is used when your GPIO line
20 - gpio-keys-polled: drivers/input/keyboard/gpio_keys_polled.c is used when your
21 GPIO line cannot generate interrupts, so it needs to be periodically polled
26 mouse cable and connect the wires to GPIO lines or solder a mouse connector
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| /Documentation/devicetree/bindings/fsi/ |
| D | fsi-master-gpio.txt | 1 Device-tree bindings for gpio-based FSI master driver
5 - compatible = "fsi-master-gpio";
6 - clock-gpios = <gpio-descriptor>; : GPIO for FSI clock
7 - data-gpios = <gpio-descriptor>; : GPIO for FSI data signal
10 - enable-gpios = <gpio-descriptor>; : GPIO for enable signal
11 - trans-gpios = <gpio-descriptor>; : GPIO for voltage translator enable
12 - mux-gpios = <gpio-descriptor>; : GPIO for pin multiplexing with other
14 - no-gpio-delays; : Don't add extra delays between GPIO
16 GPIO block is running at a low enough
22 compatible = "fsi-master-gpio", "fsi-master";
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| /Documentation/admin-guide/gpio/ |
| D | gpio-aggregator.rst | 3 GPIO Aggregator
6 The GPIO Aggregator provides a mechanism to aggregate GPIOs, and expose them as
13 GPIO controllers are exported to userspace using /dev/gpiochip* character
15 system permissions, on an all-or-nothing basis: either a GPIO controller is
18 The GPIO Aggregator provides access control for a set of one or more GPIOs, by
22 grab the full GPIO controller, and no longer needs to care about which GPIOs to
25 Aggregated GPIO controllers are instantiated and destroyed by writing to
28 /sys/bus/platform/drivers/gpio-aggregator/
31 Userspace may ask the kernel to instantiate an aggregated GPIO
42 is a GPIO line name,
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