Searched +full:has +full:- +full:chip +full:- +full:id (Results 1 – 25 of 116) sorted by relevance
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| /Documentation/devicetree/bindings/arm/amlogic/ |
| D | amlogic,meson-gx-ao-secure.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/arm/amlogic/amlogic,meson-gx-ao-secure.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Neil Armstrong <narmstrong@baylibre.com>
22 const: amlogic,meson-gx-ao-secure
24 - compatible
29 - const: amlogic,meson-gx-ao-secure
30 - const: syscon
35 amlogic,has-chip-id:
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| /Documentation/devicetree/bindings/mips/ |
| D | mscc.txt | 7 - compatible: "mscc,ocelot"
12 o CPU chip regs:
14 The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
15 functionalities: chip ID, general purpose register for software use, reset
19 - compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
20 - reg : Should contain registers location and length
24 compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
31 The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
36 - compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
37 - reg : Should contain registers location and length
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| /Documentation/ABI/testing/ |
| D | sysfs-driver-jz4780-efuse | 1 What: /sys/devices/*/<our-device>/nvmem
4 Description: read-only access to the efuse on the Ingenic JZ4780 SoC
5 The SoC has a one time programmable 8K efuse that is
11 0x008 128 bit Ingenic Chip ID
12 0x018 128 bit Customer ID
19 Users: any user space application which wants to read the Chip
20 and Customer ID
|
| D | sysfs-devices-soc | 5 The /sys/devices/ directory contains a sub-directory for each
6 System-on-Chip (SoC) device on a running platform. Information
12 It has been agreed that if an SoC device exists, its supported
19 Read-only attribute common to all SoCs. Contains the SoC machine
26 Read-only attribute common to all SoCs. Contains SoC family name
39 scheme has been defined.
47 For example, ARM has identity code 0x7F 0x7F 0x7F 0x7F 0x3B,
57 Read-only attribute supported by most SoCs. Contains the SoC's
64 Read-only attribute supported by most SoCs. In the case of
65 ST-Ericsson's chips this contains the SoC serial number.
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| /Documentation/hwmon/ |
| D | sis5595.rst | 10 Addresses scanned: ISA in PCI-space encoded address
18 - Kyösti Mälkki <kmalkki@cc.hut.fi>,
19 - Mark D. Studebaker <mdsxyz123@yahoo.com>,
20 - Aurelien Jarno <aurelien@aurel32.net> 2.6 port
22 SiS southbridge has a LM78-like chip integrated on the same IC.
28 Version PCI ID PCI Revision
36 "blacklist" PCI ID and refuse to load.
39 NOT SUPPORTED PCI ID BLACKLIST PCI ID
55 -----------------
69 -----------
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| D | w83791d.rst | 10 Addresses scanned: I2C 0x2c - 0x2f
12 Datasheet: http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/W83791D_W83791Gb.pdf
22 - Frodo Looijaard <frodol@dds.nl>,
23 - Philip Edelbrock <phil@netroedge.com>,
24 - Mark Studebaker <mdsxyz123@yahoo.com>
28 - Shane Huang (Winbond),
29 - Rudolf Marek <r.marek@assembler.cz>
33 - Sven Anders <anders@anduras.de>
34 - Marc Hulsman <m.hulsman@tudelft.nl>
37 -----------------
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| D | w83792d.rst | 10 Addresses scanned: I2C 0x2c - 0x2f
19 -----------------
24 Use 'init=0' to bypass initializing the chip.
29 a certain chip. Example usage is `force_subclients=0,0x2f,0x4a,0x4b`
30 to force the subclients of chip 0x2f on bus 0 to i2c addresses
35 -----------
39 Detection of the chip can sometimes be foiled because it can be in an
40 internal state that allows no clean access (Bank with ID register is not
41 currently selected). If you know the address of the chip, use a 'force'
42 parameter; this will put it into a more well-behaved state first.
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| /Documentation/devicetree/bindings/mtd/ |
| D | jedec,spi-nor.txt | 4 - #address-cells, #size-cells : Must be present if the device has sub-nodes
6 - compatible : May include a device-specific string consisting of the
7 manufacturer and name of the chip. A list of supported chip
9 Must also include "jedec,spi-nor" for any SPI NOR flash that can
10 be identified by the JEDEC READ ID opcode (0x9F).
12 Supported chip names:
50 The following chip names have been used historically to
52 JEDEC READ ID opcode (0x9F):
53 m25p05-nonjedec
54 m25p10-nonjedec
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| D | mtd-physmap.txt | 1 CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
6 - compatible : should contain the specific model of mtd chip(s)
7 used, if known, followed by either "cfi-flash", "jedec-flash",
8 "mtd-ram" or "mtd-rom".
9 - reg : Address range(s) of the mtd chip(s)
11 non-identical chips can be described in one node.
12 - bank-width : Width (in bytes) of the bank. Equal to the
14 - device-width : (optional) Width of a single mtd chip. If
15 omitted, assumed to be equal to 'bank-width'.
16 - #address-cells, #size-cells : Must be present if the device has
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| /Documentation/devicetree/bindings/arm/ |
| D | arm,vexpress-juno.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
11 - Linus Walleij <linus.walleij@linaro.org>
15 multicore Cortex-A class systems. The Versatile Express family contains both
37 further subvariants are released of the core tile, even more fine-granular
45 - description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
46 in MPCore configuration in a test chip on the core tile. See ARM
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-sprd-adi.txt | 3 ADI is the abbreviation of Anolog-Digital interface, which is used to access
4 analog chip (such as PMIC) from digital chip. ADI controller follows the SPI
8 ADI controller has 50 channels including 2 software read/write channels and
9 48 hardware channels to access analog chip. For 2 software read/write channels,
10 users should set ADI registers to access analog chip. For hardware channels,
12 which means we can just link one analog chip address to one hardware channel,
13 then users can access the mapped analog chip address by this hardware channel
16 Thus we introduce one property named "sprd,hw-channels" to configure hardware
17 channels, the first value specifies the hardware channel id which is used to
19 the analog chip address where user want to access by hardware components.
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| /Documentation/devicetree/bindings/pwm/ |
| D | pwm-sifive.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yash Shah <yash.shah@sifive.com>
12 - Sagar Kadam <sagar.kadam@sifive.com>
13 - Paul Walmsley <paul.walmsley@sifive.com>
18 run at the same period. The period also has significant restrictions on
21 numbers can be found here -
23 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
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| /Documentation/w1/masters/ |
| D | ds2490.rst | 13 -----------
15 The Maxim/Dallas Semiconductor DS2490 is a chip
16 which allows to build USB <-> W1 bridges.
18 DS9490(R) is a USB <-> W1 bus master device
19 which has 0x81 family ID integrated chip and DS2490
20 low-level operational chip.
24 - The weak pullup current is a minimum of 0.9mA and maximum of 6.0mA.
25 - The 5V strong pullup is supported with a minimum of 5.9mA and a
27 - The hardware will detect when devices are attached to the bus on the
31 - The number of USB bus transactions could be reduced if w1_reset_send
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfram Sang <wolfram@the-dreams.de>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - const: i2c-gpio
20 sda-gpios:
24 from <dt-bindings/gpio/gpio.h> since the signal is by definition
28 scl-gpios:
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| /Documentation/devicetree/bindings/fsi/ |
| D | fsi.txt | 4 The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
6 nodes to probed engines. This allows for fsi engines to expose non-probeable
8 that is an I2C master - the I2C bus can be described by the device tree under
13 the fsi-master-* binding specifications.
18 fsi-master {
19 /* top-level of FSI bus topology, bound to an FSI master driver and
22 fsi-slave@<link,id> {
26 fsi-slave-engine@<addr> {
32 fsi-slave-engine@<addr> {
39 Note that since the bus is probe-able, some (or all) of the topology may
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| /Documentation/networking/device_drivers/wan/ |
| D | z8530book.rst | 13 services using this chip.
25 on the chip (each chip has two channels).
28 chip is interface to the I/O and interrupt facilities of the host
29 machine but not to the DMA subsystem. When running PIO the Z8530 has
34 The DMA mode supports the chip when it is configured to use dual DMA
38 noting here that many PC machines hang or crash when the chip is driven
54 Having identified the chip you need to fill in a struct z8530_dev,
55 which describes each chip. This object must exist until you finally
58 interrupt number of the chip. (Each chip has a single interrupt source
61 :c:func:`z8530_interrupt()`. The device id should be set to the
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| /Documentation/i2c/muxes/ |
| D | i2c-mux-gpio.rst | 2 Kernel driver i2c-mux-gpio
8 -----------
10 i2c-mux-gpio is an i2c mux driver providing access to I2C bus segments
15 ---------- ---------- Bus segment 1 - - - - -
16 | | SCL/SDA | |-------------- | |
17 | |------------| |
19 | Linux | GPIO 1..N | MUX |--------------- Devices
20 | |------------| | | |
22 | | | |---------------| |
23 ---------- ---------- - - - - -
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| /Documentation/devicetree/bindings/gpio/ |
| D | qcom,wcd934x-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/qcom,wcd934x-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm Technologies Inc WCD9340/WCD9341 Audio Codec has integrated
14 gpio controller to control 5 gpios on the chip.
19 - qcom,wcd9340-gpio
20 - qcom,wcd9341-gpio
25 gpio-controller: true
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| /Documentation/firmware-guide/acpi/ |
| D | gpio-properties.rst | 1 .. SPDX-License-Identifier: GPL-2.0
31 ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
34 Package () {"reset-gpios", Package() {^BTH, 1, 1, 0 }},
35 Package () {"shutdown-gpios", Package() {^BTH, 0, 0, 0 }},
45 The device that has _CRS containing GpioIo()/GpioInt() resources,
59 must be 0. GpioInt() resource has its own means of defining it.
61 In our Bluetooth example the "reset-gpios" refers to the second GpioIo()
75 assuming non-active (Polarity = !Pull Bias)
77 Down High as low, assuming non-active
78 Up Low as high, assuming non-active
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| /Documentation/devicetree/bindings/mailbox/ |
| D | ti,message-manager.txt | 4 The Texas Instruments' Message Manager is a mailbox controller that has
5 configurable queues selectable at SoC(System on Chip) integration. The Message
7 "proxies" - each instance is unidirectional and is instantiated at SoC
13 --------------------
14 - compatible: Shall be: "ti,k2g-message-manager"
15 - reg-names queue_proxy_region - Map the queue proxy region.
16 queue_state_debug_region - Map the queue state debug
18 - reg: Contains the register map per reg-names.
19 - #mbox-cells Shall be 2. Contains the queue ID and proxy ID in that
21 - interrupt-names: Contains interrupt names matching the rx transfer path
[all …]
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| /Documentation/driver-api/ |
| D | pwm.rst | 15 ----------------
19 Instead of referring to a PWM device via its unique ID, board setup code
24 PWM_LOOKUP("tegra-pwm", 0, "pwm-backlight", NULL,
36 ----------
45 After being requested, a PWM has to be configured using::
62 PWM arguments are usually platform-specific and allows the PWM user to only
73 -----------------------------------
77 /sys/class/pwm/. Each probed PWM controller/chip will be exported as
78 pwmchipN, where N is the base of the PWM chip. Inside the directory you
82 The number of PWM channels this chip supports (read-only).
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| /Documentation/userspace-api/media/v4l/ |
| D | ext-ctrls-flash.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _flash-controls:
17 .. _flash-controls-use-cases:
24 ------------------------------------------
35 ----------------------------------------
37 The synchronised LED flash is pre-programmed by the host (power and
46 ------------------
52 .. _flash-control-id:
55 -----------------
61 Defines the mode of the flash LED, the high-power white LED attached
[all …]
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| /Documentation/devicetree/bindings/x86/ |
| D | ce4100.txt | 2 ---------------------------
5 format: <vendor>,<chip>-<device>.
11 -------------
14 #address-cells = <1>;
15 #size-cells = <0>;
34 - device_type
37 - reg
38 Local APIC ID, the unique number assigned to each processor by
42 ------------
44 This node describes the in-core peripherals. Required property:
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| /Documentation/admin-guide/media/ |
| D | cx88.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 This is a v4l2 device driver for the cx2388x chip.
12 --------------
15 - Works.
16 - Overlay isn't supported.
19 - Works. The TV standard detection is made by the driver, as the
20 hardware has bugs to auto-detect.
21 - audio data dma (i.e. recording without loopback cable to the
22 sound card) is supported via cx88-alsa.
25 - Works.
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| /Documentation/virt/kvm/devices/ |
| D | mpic.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_FSL_MPIC_20 Freescale MPIC v2.0
10 - KVM_DEV_TYPE_FSL_MPIC_42 Freescale MPIC v4.2
20 KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)
25 KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)
28 must be 4-byte aligned.
33 KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)
37 For edge-triggered interrupts: Writing 1 is considered an activating
39 signaled edge has not been acknowledged, and 0 otherwise.
47 be instantiated. Once that device has been created, it's available as
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