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/Documentation/devicetree/bindings/arc/
Darchs-pct.txt4 CPU and cache events like cache misses and hits. Like conventional PCT there
Dpct.txt4 CPU and cache events like cache misses and hits. Like conventional PCT there
/Documentation/trace/
Dkprobetrace.rst148 You can check the total number of probe hits and probe miss-hits via
150 The first column is event name, the second is the number of probe hits,
151 the third is the number of probe miss-hits.
255 Each line shows when the kernel hits an event, and <- SYMBOL means kernel
Dhistogram.rst19 aggregates event hits into a hash table keyed on one or more trace
36 event hits. If 'values' isn't specified, an implicit 'hitcount'
52 name, and trigger hits will update this common data. Only triggers
117 of hits that were ignored. The size should be a power of 2 between
276 Hits: 4610
290 totals for the run. The 'Hits' field shows the total number of
293 shows the number of hits that were dropped because the number of
302 every trigger implicitly keeps a count of the total number of hits
358 Hits: 4775
407 Hits: 109928
[all …]
Duprobetracer.rst81 You can check the total number of probe hits per event via
83 the second is the event name, the third is the number of probe hits.
Dkprobes.rst68 When a CPU hits the breakpoint instruction, a trap occurs, the CPU's
569 so keep this in mind if you're not seeing the probe hits you expect.
581 probe handler. If a probe handler hits a probe, that second probe's
658 microseconds to process. Specifically, a benchmark that hits the same
660 million hits per second, depending on the architecture. A return-probe
Devents.rst542 This command aggregates event hits into a hash table keyed on one or
/Documentation/admin-guide/device-mapper/
Dcache.rst95 forwarded to the origin device; additionally, write hits cause cache
240 <#read hits> <#read misses> <#write hits> <#write misses>
255 #read hits Number of times a READ bio has been mapped
259 #write hits Number of times a WRITE bio has been mapped
/Documentation/admin-guide/hw-vuln/
Dmultihit.rst6 instruction fetch hits multiple entries in the instruction TLB. This can
109 the possibility of multiple hits.
118 the nested guest can trigger multiple iTLB hits by modifying its own
/Documentation/ABI/testing/
Dsysfs-block-bcache28 For backing devices: integer number of full cache hits,
41 For backing devices: cache hits as a percentage.
/Documentation/fb/
Dcmap_xfbdev.rst39 colormap. For example, Xfbdev hits the following:
/Documentation/devicetree/bindings/arm/
Dpmu.yaml15 and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
/Documentation/x86/
Dresctrl_ui.rst489 fill, and from that point on will only serve cache hits. The cache
514 the region continues to serve cache hits.
577 hits and misses.
594 residency (cache hits and misses) measurement captured in the
598 residency (cache hits and misses) measurement captured in the
634 Hits: 8192
638 Example of cache hits/misses debugging
641 cache of a platform. Here is how we can obtain details of the cache hits
660 pseudo_lock_mea-1672 [002] .... 3132.860500: pseudo_lock_l2: hits=4097 miss=0
/Documentation/admin-guide/cgroup-v1/
Dmemory.rst73 memory.failcnt show the number of memory usage hits limits
74 memory.memsw.failcnt show the number of memory+Swap hits limits
96 hits limits
102 hits limits
255 **What happens when a cgroup hits memory.memsw.limit_in_bytes**
257 When a cgroup hits memory.memsw.limit_in_bytes, it's useless to do swap-out
375 triggered for a cgroup when it hits K while staying below U, which makes
623 hit its limit. When a memory cgroup hits a limit, failcnt increases and
/Documentation/devicetree/bindings/i2c/
Di2c-demux-pinctrl.txt8 if your current runtime configuration hits an errata of the internal IP core.
/Documentation/admin-guide/pm/
Dcpuidle.rst366 by the ``CPUIdle`` driver: ``hits``, ``misses`` and ``early_hits``.
368 The ``hits`` and ``misses`` metrics measure the likelihood that a given idle
374 them "matches" the sleep length). The ``hits`` metric is increased if the
393 to the sleep length. Then, the ``hits`` and ``misses`` metrics of that idle
394 state are compared with each other and it is preselected if the ``hits`` one is
403 latency within the constraint is preselected without consulting the ``hits``,
/Documentation/driver-api/md/
Draid5-cache.rst62 filesystems) right after the data hits cache disk. The data is flushed to raid
/Documentation/scheduler/
Dsched-bwc.rst136 should also be considered, especially when single core usage hits 100%. If you
/Documentation/input/devices/
Dntrig.rst93 events until it hits thresholds and begins propagating. In the interest in
/Documentation/timers/
Dtimekeeping.rst153 independently on each CPU without any synchronization performance hits.
/Documentation/admin-guide/
Dbcache.rst499 Hits and misses are counted per individual IO as bcache sees them; a
503 Hits and misses for IO that is intended to skip the cache are still counted,
/Documentation/locking/
Dww-mutex-design.rst261 when the dynamic locking step hits -EDEADLK we also need to unlock all the
/Documentation/devicetree/bindings/fpga/
Dfpga-region.txt22 This device tree binding document hits some of the high points of FPGA usage and
/Documentation/scsi/
Dscsi_mid_low_api.rst186 scsi_host_put() when the reference count hits zero.
/Documentation/block/
Dbiodoc.rst470 atomic_t bi_cnt; /* pin count: free when it hits zero */

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