Searched +full:input +full:- +full:enable (Results 1 – 25 of 294) sorted by relevance
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | nxp,lpc1850-scu.txt | 2 --------------------------------------------------------
5 - compatible : Should be "nxp,lpc1850-scu"
6 - reg : Address and length of the register set for the device
7 - clocks : Clock specifier (see clock bindings for details)
9 The lpc1850-scu driver uses the generic pin multiplexing and generic pin
10 configuration documented in pinctrl-bindings.txt.
13 - function
14 - pins
15 - bias-disable
16 - bias-pull-up
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| D | sprd,pinctrl.txt | 16 of them, so we can not make every Spreadtrum-special configuration
35 - input-enable
36 - input-disable
37 - output-high
38 - output-low
39 - bias-pull-up
40 - bias-pull-down
46 and set the pin sleep related configuration as "input-enable", which
48 input enable automatically.
54 "sprd,sleep-mode" property to set pin sleep mode.
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| D | pincfg-node.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pincfg-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
21 bias-disable:
25 bias-high-impedance:
27 description: high impedance mode ("third-state", "floating")
29 bias-bus-hold:
33 bias-pull-up:
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| D | sprd,sc9860-pinctrl.txt | 7 - compatible: Must be "sprd,sc9860-pinctrl".
8 - reg: The register address of pin controller device.
9 - pins : An array of strings, each string containing the name of a pin.
12 - function: A string containing the name of the function, values must be
14 - drive-strength: Drive strength in mA. Supported values: 2, 4, 6, 8, 10,
16 - input-schmitt-disable: Enable schmitt-trigger mode.
17 - input-schmitt-enable: Disable schmitt-trigger mode.
18 - bias-disable: Disable pin bias.
19 - bias-pull-down: Pull down on pin.
20 - bias-pull-up: Pull up on pin. Supported values: 20000 for pull-up resistor
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| D | brcm,bcm11351-pinctrl.txt | 10 - compatible: Must be "brcm,bcm11351-pinctrl"
11 - reg: Base address of the PAD Controller register block and the size
17 compatible = "brcm,bcm11351-pinctrl";
27 Each pin configuration node is a sub-node of the pin controller node and is a
31 Please refer to the pinctrl-bindings.txt in this directory for details of the
45 details generic pin config properties, please refer to pinctrl-bindings.txt
46 and <include/linux/pinctrl/pinconfig-generic.h>.
54 - pins: Multiple strings. Specifies the name(s) of one or more pins to
59 - function: String. Specifies the pin mux selection. Values
61 - input-schmitt-enable: No arguments. Enable schmitt-trigger mode.
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| D | microchip,pic32-pinctrl.txt | 3 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
4 ../interrupt-controller/interrupts.txt for generic information regarding
12 - compatible: "microchip,pic32mada-pinctrl"
13 - reg: Address range of the pinctrl registers.
14 - clocks: Clock specifier (see clock bindings for details)
16 Required properties for pin configuration sub-nodes:
17 - pins: List of pins to which the configuration applies.
19 Optional properties for pin configuration sub-nodes:
20 ----------------------------------------------------
21 - function: Mux function for the specified pins.
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| D | nvidia,tegra194-pinmux.txt | 4 - compatible: "nvidia,tegra194-pinmux"
5 - reg: Should contain a list of base address and size pairs for:
6 - first entry: The APB_MISC_GP_*_PADCTRL registers (pad control)
7 - second entry: The PINMUX_AUX_* registers (pinmux)
9 Please refer to pinctrl-bindings.txt in this directory for details of the
17 parameters, such as pull-up, tristate, drive strength, etc.
21 include/dt-binding/pinctrl/pinctrl-tegra.h.
23 Required subnode-properties:
24 - nvidia,pins : An array of strings. Each string contains the name of a pin or
27 Optional subnode-properties:
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| D | pinctrl-mt6797.txt | 6 - compatible: Value should be one of the following.
7 "mediatek,mt6797-pinctrl", compatible with mt6797 pinctrl.
8 - reg: Should contain address and size for gpio, iocfgl, iocfgb,
10 - reg-names: An array of strings describing the "reg" entries. Must
12 - gpio-controller: Marks the device node as a gpio controller.
13 - #gpio-cells: Should be two. The first cell is the gpio pin number
17 - interrupt-controller: Marks the device node as an interrupt controller.
18 - #interrupt-cells: Should be two.
19 - interrupts : The interrupt outputs from the controller.
21 Please refer to pinctrl-bindings.txt in this directory for details of the
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| D | pinctrl-mt8183.txt | 6 - compatible: value should be one of the following.
7 "mediatek,mt8183-pinctrl", compatible with mt8183 pinctrl.
8 - gpio-controller : Marks the device node as a gpio controller.
9 - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
12 - gpio-ranges : gpio valid number range.
13 - reg: physical address base for gpio base registers. There are 10 GPIO
17 - reg-names: gpio base register names. There are 10 gpio base register
20 - interrupt-controller: Marks the device node as an interrupt controller
21 - #interrupt-cells: Should be two.
22 - interrupts : The interrupt outputs to sysirq.
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| D | pinctrl-single.txt | 1 One-register-per-pin type device tree based pinctrl driver
4 - compatible : "pinctrl-single" or "pinconf-single".
5 "pinctrl-single" means that pinconf isn't supported.
6 "pinconf-single" means that generic pinconf is supported.
8 - reg : offset and length of the register set for the mux registers
10 - #pinctrl-cells : number of cells in addition to the index, set to 1
11 for pinctrl-single,pins and 2 for pinctrl-single,bits
13 - pinctrl-single,register-width : pinmux register access width in bits
15 - pinctrl-single,function-mask : mask of allowed pinmux function bits
19 - pinctrl-single,function-off : function off mode for disabled state if
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| D | pinctrl-mt8192.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8192.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8192-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
38 reg-names:
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| /Documentation/devicetree/bindings/mfd/ |
| D | as3722.txt | 4 -------------------
5 - compatible: Must be "ams,as3722".
6 - reg: I2C device address.
7 - interrupt-controller: AS3722 has internal interrupt controller which takes the
8 interrupt request from internal sub-blocks like RTC, regulators, GPIOs as well
9 as external input.
10 - #interrupt-cells: Should be set to 2 for IRQ number and flags.
12 of AS3722 are defined at dt-bindings/mfd/as3722.h
14 interrupts.txt, using dt-bindings/irq.
17 --------------------
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| D | tps65910.txt | 4 - compatible: "ti,tps65910" or "ti,tps65911"
5 - reg: I2C slave address
6 - interrupts: the interrupt outputs of the controller
7 - #gpio-cells: number of cells to describe a GPIO, this should be 2.
10 - gpio-controller: mark the device as a GPIO controller
11 - #interrupt-cells: the number of cells to describe an IRQ, this should be 2.
14 Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
15 - regulators: This is the list of child nodes that specify the regulator
20 The regulator is matched with the regulator-compatible.
22 The valid regulator-compatible values are:
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| /Documentation/devicetree/bindings/arm/ |
| D | atmel-sysregs.txt | 4 - compatible: Should be "atmel,sama5d2-chipid"
5 - reg : Should contain registers location and length
8 - compatible: Should be "atmel,at91sam9260-pit"
9 - reg: Should contain registers location and length
10 - interrupts: Should contain interrupt for the PIT which is the IRQ line
14 - compatible: Should be "microchip,sam9x60-pit64b"
15 - reg: Should contain registers location and length
16 - interrupts: Should contain interrupt for PIT64B timer
17 - clocks: Should contain the available clock sources for PIT64B timer.
20 - compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd"
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| /Documentation/devicetree/bindings/power/supply/ |
| D | summit,smb347-charger.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/power/supply/summit,smb347-charger.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - David Heidelberg <david@ixit.cz>
11 - Dmitry Osipenko <digetx@gmail.com>
16 - summit,smb345
17 - summit,smb347
18 - summit,smb358
26 monitored-battery:
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| /Documentation/devicetree/bindings/regulator/ |
| D | tps62360-regulator.txt | 4 - compatible: Must be one of the following.
9 - reg: I2C slave address
12 - ti,enable-vout-discharge: Enable output discharge. This is boolean value.
13 - ti,enable-pull-down: Enable pull down. This is boolean value.
14 - ti,vsel0-gpio: GPIO for controlling VSEL0 line.
17 - ti,vsel1-gpio: Gpio for controlling VSEL1 line.
20 - ti,vsel0-state-high: Initial state of vsel0 input is high.
22 - ti,vsel1-state-high: Initial state of vsel1 input is high.
33 regulator-name = "tps62361-vout";
34 regulator-min-microvolt = <500000>;
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| D | as3722-regulator.txt | 5 --------------------
6 The input supply of regulators are the optional properties on the
7 regulator node. The AS3722 is having 7 DCDC step-down regulators as
8 sd[0-6], 10 LDOs as ldo[0-7], ldo[9-11]. The input supply of these
10 vsup-sd2-supply: Input supply for SD2.
11 vsup-sd3-supply: Input supply for SD3.
12 vsup-sd4-supply: Input supply for SD4.
13 vsup-sd5-supply: Input supply for SD5.
14 vin-ldo0-supply: Input supply for LDO0.
15 vin-ldo1-6-supply: Input supply for LDO1 and LDO6.
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| D | richtek,rtmv20-regulator.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rtmv20-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
15 (Enable/Fail), Enable pin to turn chip on, and Fail pin as fault indication.
17 the others for outputs (fsin1 and fsin2). Strobe input to start the current
18 supply, vsync input from IR camera, and fsin1/fsin2 output for the optional.
27 wakeup-source: true
32 enable-gpios:
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| /Documentation/devicetree/bindings/rtc/ |
| D | rtc-omap.txt | 4 - compatible:
5 - "ti,da830-rtc" - for RTC IP used similar to that on DA8xx SoC family.
6 - "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family.
7 This RTC IP has special WAKE-EN Register to enable
11 - "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family.
12 - reg: Address range of rtc register set
13 - interrupts: rtc timer, alarm interrupts in order
16 - system-power-controller: whether the rtc is controlling the system power
18 - clocks: Any internal or external clocks feeding in to rtc
19 - clock-names: Corresponding names of the clocks
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| /Documentation/devicetree/bindings/clock/ |
| D | clk-palmas-clk32kg-clocks.txt | 5 This binding uses the common clock binding ./clock-bindings.txt.
8 - compatible : "ti,palmas-clk32kg" for clk32kg clock
9 "ti,palmas-clk32kgaudio" for clk32kgaudio clock
10 - #clock-cells : shall be set to 0.
13 - ti,external-sleep-control: The external enable input pins controlled the
14 enable/disable of clocks. The external enable input pins ENABLE1,
22 dt-bindings/mfd/palmas.h
25 #include <dt-bindings/mfd/palmas.h>
30 compatible = "ti,palmas-clk32kg";
31 #clock-cells = <0>;
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| D | vt8500.txt | 1 Device Tree Clock bindings for arch-vt8500
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
13 "via,vt8500-device-clock" - for a VT/WM device clock
16 - reg : shall be the control register offset from PMC base for the pll clock.
17 - clocks : shall be the input parent clock phandle for the clock. This should
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| /Documentation/driver-api/mei/ |
| D | mei.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 resource (Co-processor) residing inside certain Intel chipsets. The Intel ME
18 each client has its own protocol. The protocol is message-based with a
50 .. code-block:: C
83 -------------------------
86 .. code-block:: none
96 struct mei_connect_client_data - contain the following
97 Input field:
99 in_client_uuid - GUID of the FW Feature that needs
102 out_client_properties - Client Properties: MTU and Protocol Version.
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| /Documentation/devicetree/bindings/display/ti/ |
| D | ti,opa362.txt | 4 - compatible: "ti,opa362"
5 - enable-gpios: enable/disable output gpio
8 - Video port 0 for opa362 input
9 - Video port 1 for opa362 output
15 enable-gpios = <&gpio1 23 0>; /* GPIO to enable video out amplifier */
18 #address-cells = <1>;
19 #size-cells = <0>;
24 remote-endpoint = <&venc_out>;
31 remote-endpoint = <&tv_connector_in>;
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| /Documentation/devicetree/bindings/leds/ |
| D | leds-lm3532.txt | 1 * Texas Instruments - lm3532 White LED driver with ambient light sensing
4 The LM3532 provides the 3 high-voltage, low-side current sinks. The device is
5 programmable over an I2C-compatible interface and has independent
11 each with 32 internal voltage setting resistors, 8-bit logarithmic and linear
16 - compatible : "ti,lm3532"
17 - reg : I2C slave address
18 - #address-cells : 1
19 - #size-cells : 0
22 - enable-gpios : gpio pin to enable (active high)/disable the device.
23 - ramp-up-us - The Run time ramp rates/step are from one current
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| /Documentation/devicetree/bindings/input/ |
| D | ti,drv260x.txt | 1 * Texas Instruments - drv260x Haptics driver family
4 - compatible - One of:
5 "ti,drv2604" - DRV2604
6 "ti,drv2605" - DRV2605
7 "ti,drv2605l" - DRV2605L
8 - reg - I2C slave address
9 - vbat-supply - Required supply regulator
10 - mode - Power up mode of the chip (defined in include/dt-bindings/input/ti-drv260x.h)
11 DRV260X_LRA_MODE - Linear Resonance Actuator mode (Piezoelectric)
12 DRV260X_LRA_NO_CAL_MODE - This is a LRA Mode but there is no calibration
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