Searched full:instruction (Results 1 – 25 of 158) sorted by relevance
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| /Documentation/virt/kvm/ |
| D | s390-pv.rst | 26 the behavior of the SIE instruction. A new format 4 state description
48 of an instruction emulation by KVM, e.g. we can never inject a
63 Instruction emulation
65 With the format 4 state description for PVMs, the SIE instruction already
67 to interpret every instruction, but needs to hand some tasks to KVM;
71 Instruction Data Area (SIDA), the Interception Parameters (IP) and the
73 the instruction data, such as I/O data structures, are filtered.
74 Instruction data is copied to and from the SIDA when needed. Guest
78 Only GR values needed to emulate an instruction will be copied into this
82 the bytes of the instruction text, but with pre-set register values
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| D | hypercalls.rst | 9 instruction. The hypervisor can replace it with instructions that are
21 S390 uses diagnose instruction as hypercall (0x500) along with hypercall
36 KVM hypercalls use the HYPCALL instruction with code 0 and the hypercall
95 execute HLT instruction once it has busy-waited for more than a threshold
96 time-interval. Execution of HLT instruction would cause the hypervisor to put
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| D | ppc-pv.rst | 82 instruction reads the first field of the magic page::
146 guest. Implementing any of those mappings is optional, as the instruction traps
188 or store instruction can deliver. To enable patching of those, we keep some
193 2) patch that code to fit the emulated instruction
195 4) patch the original instruction to branch to the new code
198 instruction. This allows us to check for pending interrupts when setting EE=1
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| /Documentation/arm64/ |
| D | legacy_instructions.rst | 7 the architecture. The infrastructure code uses undefined instruction
9 the instruction execution in hardware.
18 Generates undefined instruction abort. Default for instructions that
25 usage of emulated instruction is traced as well as rate limited
38 The default mode depends on the status of the instruction in the
42 Note: Instruction emulation may not be possible in all cases. See
43 individual instruction notes for further information.
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| /Documentation/staging/ |
| D | lzo.rst | 22 the operands for the instruction, whose size and position depend on the
23 opcode and on the number of literals copied by previous instruction. The
59 After any instruction except the large literal copy, 0, 1, 2 or 3 literals
60 are copied before starting the next instruction. The number of literals that
61 were copied may change the meaning and behaviour of the next instruction. In
62 practice, only one instruction needs to know whether 0, less than 4, or more
65 generally encoded in the last two bits of the instruction but may also be
69 instruction may encode this distance (0001HLLL), it takes one LE16 operand
100 0..16 : follow regular instruction encoding, see below. It is worth
120 Instruction encoding::
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| /Documentation/trace/coresight/ |
| D | coresight.rst | 22 "Sources" generate a compressed stream representing the processor instruction
359 comparator with "_stext" and "_etext", essentially tracing any instruction
399 Instruction 106378866 0x8026B53C E52DE004 false PUSH {lr}
400 Instruction 0 0x8026B540 E24DD00C false SUB sp,sp,#0xc
401 Instruction 0 0x8026B544 E3A03000 false MOV r3,#0
402 Instruction 0 0x8026B548 E58D3004 false STR r3,[sp,#4]
403 Instruction 0 0x8026B54C E59D3004 false LDR r3,[sp,#4]
404 Instruction 0 0x8026B550 E3530004 false CMP r3,#4
405 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
406 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
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| /Documentation/trace/ |
| D | kprobes.rst | 38 any instruction in the kernel. A return probe fires when a specified
65 instruction and replaces the first byte(s) of the probed instruction
66 with a breakpoint instruction (e.g., int3 on i386 and x86_64).
68 When a CPU hits the breakpoint instruction, a trap occurs, the CPU's
74 Next, Kprobes single-steps its copy of the probed instruction.
75 (It would be simpler to single-step the actual instruction in place,
77 instruction. This would open a small time window when another CPU
80 After the instruction is single-stepped, Kprobes executes the
82 Execution then continues with the instruction following the probepoint.
88 register set, including instruction pointer. This operation requires
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| /Documentation/arm/nwfpe/ |
| D | notes.rst | 11 often uses an stfe instruction to save f4 on the stack upon entry to a
12 function, and an ldfe instruction to restore it before returning.
18 This is a side effect of the stfe instruction. The double in f4 had to be
32 in extended precision, due to the stfe instruction used to save f4 in log(y).
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| /Documentation/powerpc/ |
| D | syscall64-abi.rst | 10 The syscall is made with the sc instruction, and returns with execution
11 continuing at the instruction following the sc instruction.
14 scv 0 instruction is an alternative that may provide better performance,
32 - For the sc instruction, both a value and an error condition are returned.
38 - For the scv 0 instruction, the return value indicates failure if it is
53 | For the sc instruction, differences with the ELF ABI |
62 | For the scv 0 instruction, differences with the ELF ABI |
106 performed with the sc instruction, if it is 0x3000 then the system call was
107 performed with the scv 0 instruction.
134 The vsyscall is performed with a branch-with-link instruction to the vsyscall
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| D | dscr.rst | 64 works, as it is emulated following an illegal instruction exception
69 all mfspr instruction based read attempts will get emulated and returned
70 where as the first mtspr instruction based write attempts will enable
82 (1) mtspr instruction (SPR number 0x03)
83 (2) mtspr instruction (SPR number 0x11)
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| /Documentation/devicetree/bindings/watchdog/ |
| D | microchip,pic32-dmt.txt | 4 malfunction. It is a free-running instruction fetch timer, which is clocked
5 whenever an instruction fetch occurs until a count match occurs.
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| /Documentation/filesystems/spufs/ |
| D | spu_run.rst | 28 uled to a physical SPU, it starts execution at the instruction pointer
37 When spu_run returns, the current value of the SPU instruction pointer
62 optionally a 14 bit code returned from the stop-and-signal instruction
78 SPU has tried to execute an invalid instruction.
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| /Documentation/bpf/ |
| D | bpf_design_QA.rst | 18 Q: Is BPF a generic instruction set similar to x64 and arm64?
26 BPF is generic instruction set *with* C calling convention.
33 which is written in C, hence BPF defines instruction set compatible
46 as arguments. BPF is not a standalone instruction set.
49 Q: Can BPF programs access instruction pointer or return address?
100 calls, a limit to the number of the verifier states per instruction,
116 Instruction level questions
122 Q: How come LD_ABS and LD_IND instruction are present in BPF whereas
137 Q: Why BPF_DIV instruction doesn't map to x64 div?
185 is required, and insert an explicit zero-extension (zext) instruction
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| /Documentation/devicetree/bindings/nios2/ |
| D | nios2.txt | 18 - icache-line-size: Contains instruction line size.
20 - icache-size: Contains instruction cache size.
28 - altr,has-initda: Specifies CPU support initda instruction, should be 1.
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| /Documentation/arm/ |
| D | swp_emulation.rst | 1 Software emulation of deprecated SWP instruction (CONFIG_SWP_EMULATE)
8 instructions, triggering an undefined instruction exception when executed.
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| D | kernel_mode_neon.rst | 36 instruction is issued, allowing the kernel to step in and perform the restore if
70 software assistance, it signals the kernel by raising an undefined instruction
72 current instruction and arguments, and emulates the instruction in software.
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| /Documentation/x86/ |
| D | tlb.rst | 10 1. Flush the entire TLB with a two-instruction sequence. This is
14 2. Use the invlpg instruction to invalidate a single page at a
42 invlpg instruction (or instructions _near_ it) show up high in
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| D | entry_64.rst | 25 - system_call: syscall instruction from 64-bit code.
53 Dealing with the swapgs instruction is especially tricky. Swapgs
55 instruction is rather fragile: it must nest perfectly and only in
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| D | amd-memory-encryption.rst | 36 When SEV is enabled, instruction pages and guest page tables are always treated
42 Support for SME and SEV can be determined through the CPUID instruction. The
79 The CPU supports SME (determined through CPUID instruction).
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| D | mds.rst | 77 instruction in combination with a microcode update. The microcode clears
78 the affected CPU buffers when the VERW instruction is executed.
81 clearing. Either the modified VERW instruction or via the L1D Flush
86 If the VERW instruction with the supplied segment selector argument is
103 MD_CLEAR CPUID bit to guests, the kernel issues the VERW instruction in the
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| /Documentation/parisc/ |
| D | debugging.rst | 41 was interrupted - so if you get an interruption between the instruction
44 instruction that cleared the Q bit, if you're not it points anywhere
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| D | registers.rst | 24 CR19 Interrupt Instruction Register
72 N (Nullify next instruction) used by C code
101 Those are used in RETURN FROM INTERRUPTION AND RESTORE instruction to reduce
119 The addil instruction is hardwired to place its result in r1,
120 so if you use that instruction be aware of that.
148 the ble instruction puts the return pointer in here.
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| /Documentation/admin-guide/hw-vuln/ |
| D | srso.rst | 15 CALL instruction (i.e., an instruction predicted to be a CALL but is
17 to predict the target of a subsequent RET instruction.
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| /Documentation/admin-guide/pm/ |
| D | intel_idle.rst | 26 ``intel_idle`` uses the ``MWAIT`` instruction to inform the processor that the
28 processor's functional blocks into low-power states. That instruction takes two
33 which the support for the ``MWAIT`` instruction has been disabled (for example,
35 instruction at all.
77 ``MWAIT`` instruction is expected to be used to tell the processor that it can
130 line options forbid the use of the ``MWAIT`` instruction. If that is the case,
168 ``MWAIT`` instruction is not allowed to be used, so the initialization of
221 Typically, in a processor supporting the ``MWAIT`` instruction there are (at
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| /Documentation/core-api/ |
| D | this_cpu_ops.rst | 15 specific per cpu base and encode that operation in the instruction
72 instruction via a segment register prefix.
81 results in a single instruction::
95 The above results in the following single instruction (no lock prefix!)::
115 after the this_cpu instruction is executed. In general this means that
257 instruction.
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