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/Documentation/devicetree/bindings/interrupt-controller/
Dsnps,dw-apb-ictl.txt1 Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
3 Synopsys DesignWare provides interrupt controller IP for APB known as
4 dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
5 APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
6 controller in some SoCs, e.g. Hisilicon SD5203.
9 - compatible: shall be "snps,dw-apb-ictl"
10 - reg: physical base address of the controller and length of memory mapped
12 - interrupt-controller: identifies the node as an interrupt controller
13 - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
15 Additional required property when it's used as secondary interrupt controller:
[all …]
Dmarvell,orion-intc.txt1 Marvell Orion SoC interrupt controllers
3 * Main interrupt controller
6 - compatible: shall be "marvell,orion-intc"
7 - reg: base address(es) of interrupt registers starting with CAUSE register
8 - interrupt-controller: identifies the node as an interrupt controller
9 - #interrupt-cells: number of cells to encode an interrupt source, shall be 1
11 The interrupt sources map to the corresponding bits in the interrupt
13 - 0 maps to bit 0 of first base address,
14 - 1 maps to bit 1 of first base address,
15 - 32 maps to bit 0 of second base address, and so on.
[all …]
Dsigma,smp8642-intc.txt1 Sigma Designs SMP86xx/SMP87xx secondary interrupt controller
4 - compatible: should be "sigma,smp8642-intc"
5 - reg: physical address of MMIO region
6 - ranges: address space mapping of child nodes
7 - interrupt-controller: boolean
8 - #address-cells: should be <1>
9 - #size-cells: should be <1>
12 - reg: address of registers for this control block
13 - interrupt-controller: boolean
14 - #interrupt-cells: should be <2>, interrupt index and flags per interrupts.txt
[all …]
Dsamsung,exynos4210-combiner.txt1 * Samsung Exynos Interrupt Combiner Controller
3 Samsung's Exynos4 architecture includes a interrupt combiner controller which
4 can combine interrupt sources as a group and provide a single interrupt request
5 for the group. The interrupt request from each group are connected to a parent
6 interrupt controller, such as GIC in case of Exynos4210.
8 The interrupt combiner controller consists of multiple combiners. Up to eight
9 interrupt sources can be connected to a combiner. The combiner outputs one
10 combined interrupt for its eight interrupt sources. The combined interrupt
11 is usually connected to a parent interrupt controller.
13 A single node in the device tree is used to describe the interrupt combiner
[all …]
Dti,c64x+megamod-pic.txt1 C6X Interrupt Chips
2 -------------------
4 * C64X+ Core Interrupt Controller
6 The core interrupt controller provides 16 prioritized interrupts to the
8 Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
12 --------------------
13 - compatible: Should be "ti,c64x+core-pic";
14 - #interrupt-cells: <1>
16 Interrupt Specifier Definition
17 ------------------------------
[all …]
Dandestech,ativic32.txt1 * Andestech Internal Vector Interrupt Controller
3 The Internal Vector Interrupt Controller (IVIC) is a basic interrupt controller
5 bigger External Vector Interrupt Controller.
10 - compatible : should at least contain "andestech,ativic32".
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells: 1 cells and refer to interrupt-controller/interrupts
15 intc: interrupt-controller {
17 #interrupt-cells = <1>;
18 interrupt-controller;
Dfaraday,ftintc010.txt1 * Faraday Technologt FTINTC010 interrupt controller
3 This interrupt controller is a stock IP block from Faraday Technology found
7 - compatible: must be one of
9 "cortina,gemini-interrupt-controller" (deprecated)
10 - reg: The register bank for the interrupt controller.
11 - interrupt-controller: Identifies the node as an interrupt controller
12 - #interrupt-cells: The number of cells to define the interrupts.
13 Must be 2 as the controller can specify level or rising edge
16 interrupt-controller/interrupts.txt
20 interrupt-controller@48000000 {
[all …]
Dabilis,tb10x-ictl.txt1 TB10x Top Level Interrupt Controller
4 The Abilis TB10x SOC contains a custom interrupt controller. It performs
5 one-to-one mapping of external interrupt sources to CPU interrupts and
9 -------------------
11 - compatible: Should be "abilis,tb10x-ictl"
12 - reg: specifies physical base address and size of register range.
13 - interrupt-congroller: Identifies the node as an interrupt controller.
14 - #interrupt cells: Specifies the number of cells used to encode an interrupt
15 source connected to this controller. The value shall be 2.
16 - interrupts: Specifies the list of interrupt lines which are handled by
[all …]
Dbrcm,bcm3380-l2-intc.txt1 Broadcom BCM3380-style Level 1 / Level 2 interrupt controller
3 This interrupt controller shows up in various forms on many BCM338x/BCM63xx
6 - outputs a single interrupt signal to its interrupt controller parent
8 - contains one or more enable/status word pairs, which often appear at
11 - no atomic set/clear operations
15 - compatible: should be "brcm,bcm3380-l2-intc"
16 - reg: specifies one or more enable/status pairs, in the following format:
18 - interrupt-controller: identifies the node as an interrupt controller
19 - #interrupt-cells: specifies the number of cells needed to encode an interrupt
21 - interrupts: specifies the interrupt line in the interrupt-parent controller
[all …]
Dbrcm,bcm7120-l2-intc.txt1 Broadcom BCM7120-style Level 2 interrupt controller
3 This interrupt controller hardware is a second level interrupt controller that
4 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
7 Such an interrupt controller has the following hardware design:
9 - outputs multiple interrupts signals towards its interrupt controller parent
11 - controls how some of the interrupts will be flowing, whether they will
12 directly output an interrupt signal towards the interrupt controller parent,
13 or if they will output an interrupt signal at this 2nd level interrupt
14 controller, in particular for UARTs
16 - has one 32-bit enable word and one 32-bit status word
[all …]
Dqca,ath79-misc-intc.txt1 Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller
3 The MISC interrupt controller is a secondary controller for lower priority
4 interrupt.
7 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or
8 "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"
9 - reg: Base address and size of the controllers memory area
10 - interrupts: Interrupt specifier for the controllers interrupt.
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
19 Interrupt Controllers bindings used by client devices.
[all …]
Dmarvell,armada-8k-pic.txt1 Marvell Armada 7K/8K PIC Interrupt controller
2 ---------------------------------------------
4 This is the Device Tree binding for the PIC, a secondary interrupt
5 controller available on the Marvell Armada 7K/8K ARM64 SoCs, and
6 typically connected to the GIC as the primary interrupt controller.
9 - compatible: should be "marvell,armada-8k-pic"
10 - interrupt-controller: identifies the node as an interrupt controller
11 - #interrupt-cells: the number of cells to define interrupts on this
12 controller. Should be 1
13 - reg: the register area for the PIC interrupt controller
[all …]
Dsamsung,s3c24xx-irq.txt1 Samsung S3C24XX Interrupt Controllers
3 The S3C24XX SoCs contain a custom set of interrupt controllers providing a
4 varying number of interrupt sources. The set consists of a main- and sub-
5 controller and on newer SoCs even a second main controller.
8 - compatible: Compatible property value should be "samsung,s3c2410-irq"
9 for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later.
11 - reg: Physical base address of the controller and length of memory mapped
14 - interrupt-controller : Identifies the node as an interrupt controller
16 - #interrupt-cells : Specifies the number of cells needed to encode an
17 interrupt source. The value shall be 4 and interrupt descriptor shall
[all …]
Dmarvell,sei.txt1 Marvell SEI (System Error Interrupt) Controller
2 -----------------------------------------------
4 Marvell SEI (System Error Interrupt) controller is an interrupt
6 them to a single interrupt line (an SPI) on the parent interrupt
7 controller.
9 This interrupt controller can handle up to 64 SEIs, a set comes from the
15 - compatible: should be one of:
16 * "marvell,ap806-sei"
17 - reg: SEI registers location and length.
18 - interrupts: identifies the parent IRQ that will be triggered.
[all …]
Dmarvell,icu.txt1 Marvell ICU Interrupt Controller
2 --------------------------------
4 The Marvell ICU (Interrupt Consolidation Unit) controller is
5 responsible for collecting all wired-interrupt sources in the CP and
6 communicating them to the GIC in the AP, the unit translates interrupt
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
17 Subnodes: Each group of interrupt is declared as a subnode of the ICU,
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
[all …]
Dsnps,archs-idu-intc.txt1 * ARC-HS Interrupt Distribution Unit
3 This optional 2nd level interrupt controller can be used in SMP configurations
9 - compatible: "snps,archs-idu-intc"
10 - interrupt-controller: This is an interrupt controller.
11 - #interrupt-cells: Must be <1> or <2>.
14 Number N of the particular interrupt line of IDU corresponds to the line N+24
15 of the core interrupt controller.
18 - bits[3:0] trigger type and level flags
19 1 = low-to-high edge triggered
20 2 = NOT SUPPORTED (high-to-low edge triggered)
[all …]
Dnxp,lpc3220-mic.txt1 * NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers
4 - compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
5 - reg: should contain IC registers location and length.
6 - interrupt-controller: identifies the node as an interrupt controller.
7 - #interrupt-cells: the number of cells to define an interrupt, should be 2.
10 IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
11 IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
12 IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
13 IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
17 - interrupts: empty for MIC interrupt controller, cascaded MIC
[all …]
Dcsky,apb-intc.txt2 C-SKY APB Interrupt Controller
5 C-SKY APB Interrupt Controller is a simple soc interrupt controller
6 on the apb bus and we only use it as root irq controller.
8 - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums.
9 - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported.
10 - csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq nums.
16 Description: Describes APB interrupt controller
20 - compatible
23 Definition: must be "csky,apb-intc"
24 "csky,dual-apb-intc"
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/Documentation/devicetree/bindings/gpio/
D8xxx_gpio.txt3 This is for the non-QE/CPM/GUTs GPIO controllers as found on
6 Every GPIO controller node must have #gpio-cells property defined,
7 this information will be used to translate gpio-specifiers.
11 The GPIO module usually is connected to the SoC's internal interrupt
12 controller, see bindings/interrupt-controller/interrupts.txt (the
13 interrupt client nodes section) for details how to specify this GPIO
14 module's interrupt.
16 The GPIO module may serve as another interrupt controller (cascaded to
17 the SoC's internal interrupt controller). See the interrupt controller
18 nodes section in bindings/interrupt-controller/interrupts.txt for
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Dintel,ixp4xx-gpio.txt3 This GPIO controller is found in the Intel IXP4xx processors.
6 The interrupt portions of the GPIO controller is hierarchical:
8 actual enabling/disabling of the interrupt line is done in the
9 main IXP4xx interrupt controller which has a 1:1 mapping for
15 The interrupt parent of this GPIO controller must be the
16 IXP4xx interrupt controller.
20 - compatible : Should be
21 "intel,ixp4xx-gpio"
22 - reg : Should contain registers location and length
23 - gpio-controller : marks this as a GPIO controller
[all …]
Dgpio-altera.txt1 Altera GPIO controller bindings
4 - compatible:
5 - "altr,pio-1.0"
6 - reg: Physical base address and length of the controller's registers.
7 - #gpio-cells : Should be 2
8 - The first cell is the gpio offset number.
9 - The second cell is reserved and is currently unused.
10 - gpio-controller : Marks the device node as a GPIO controller.
11 - interrupt-controller: Mark the device node as an interrupt controller
12 - #interrupt-cells : Should be 2. The interrupt type is fixed in the hardware.
[all …]
Dmediatek,mt7621-gpio.txt1 Mediatek MT7621 SoC GPIO controller bindings
5 We load one GPIO controller instance per bank. Also the GPIO controller can receive
10 - #gpio-cells : Should be two. The first cell is the GPIO pin number and the
11 second cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>.
13 - #interrupt-cells : Specifies the number of cells needed to encode an
14 interrupt. Should be 2. The first cell defines the interrupt number,
16 Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
17 - compatible:
18 - "mediatek,mt7621-gpio" for Mediatek controllers
19 - reg : Physical base address and length of the controller's registers
[all …]
Dbrcm,brcmstb-gpio.txt1 Broadcom STB "UPG GIO" GPIO controller
3 The controller's registers are organized as sets of eight 32-bit
5 interrupt is shared for all of the banks handled by the controller.
9 - compatible:
10 Must be "brcm,brcmstb-gpio"
12 - reg:
14 the brcmstb GPIO controller registers
16 - #gpio-cells:
17 Should be <2>. The first cell is the pin number (within the controller's
19 bit[0]: polarity (0 for active-high, 1 for active-low)
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/Documentation/devicetree/bindings/pci/
Duniphier-pcie.txt1 Socionext UniPhier PCIe host controller bindings
3 This describes the devicetree bindings for PCIe host controller implemented
6 UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core.
9 Documentation/devicetree/bindings/pci/designware-pcie.txt.
12 - compatible: Should be "socionext,uniphier-pcie".
13 - reg: Specifies offset and length of the register set for the device.
14 According to the reg-names, appropriate register sets are required.
15 - reg-names: Must include the following entries:
16 "dbi" - controller configuration registers
17 "link" - SoC-specific glue layer registers
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/Documentation/devicetree/bindings/spmi/
Dqcom,spmi-pmic-arb.txt1 Qualcomm SPMI Controller (PMIC Arbiter)
4 controller with wrapping arbitration logic to allow for multiple on-chip
7 The PMIC Arbiter can also act as an interrupt controller, providing interrupts
11 controller binding requirements for child nodes.
13 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
14 generic interrupt controller binding documentation.
17 - compatible : should be "qcom,spmi-pmic-arb".
18 - reg-names : must contain:
19 "core" - core registers
20 "intr" - interrupt controller registers
[all …]

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