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/Documentation/devicetree/bindings/edac/
Dsocfpga-eccmgr.txt8 - compatible : Should be "altr,socfpga-ecc-manager"
9 - #address-cells: must be 1
10 - #size-cells: must be 1
11 - ranges : standard definition, should translate from local addresses
17 - compatible : Should be "altr,socfpga-l2-ecc"
18 - reg : Address and size for ECC error interrupt clear registers.
19 - interrupts : Should be single bit error interrupt, then double bit error
20 interrupt. Note the rising edge type.
24 - compatible : Should be "altr,socfpga-ocram-ecc"
25 - reg : Address and size for ECC error interrupt clear registers.
[all …]
/Documentation/devicetree/bindings/interrupt-controller/
Dinterrupts.txt1 Specifying interrupt information for devices
4 1) Interrupt client nodes
5 -------------------------
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
11 properties contain a list of interrupt specifiers, one per output interrupt. The
12 format of the interrupt specifier is determined by the interrupt controller to
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
20 interrupts are routed and contains a single phandle referring to the interrupt
22 interrupt client node or in any of its parent nodes. Interrupts listed in the
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Dmarvell,icu.txt1 Marvell ICU Interrupt Controller
2 --------------------------------
4 The Marvell ICU (Interrupt Consolidation Unit) controller is
5 responsible for collecting all wired-interrupt sources in the CP and
6 communicating them to the GIC in the AP, the unit translates interrupt
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
17 Subnodes: Each group of interrupt is declared as a subnode of the ICU,
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
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Dfsl,ls-scfg-msi.txt5 - compatible: should be "fsl,<soc-name>-msi" to identify
7 "fsl,ls1021a-msi"
8 "fsl,ls1043a-msi"
9 "fsl,ls1046a-msi"
10 "fsl,ls1043a-v1.1-msi"
11 "fsl,ls1012a-msi"
12 - msi-controller: indicates that this is a PCIe MSI controller node
13 - reg: physical base address of the controller and length of memory mapped.
14 - interrupts: an interrupt to the parent interrupt controller.
16 This interrupt controller hardware is a second level interrupt controller that
[all …]
Dbrcm,bcm6345-l1-intc.txt1 Broadcom BCM6345-style Level 1 interrupt controller
3 This block is a first level interrupt controller that is typically connected
8 - 32, 64 or 128 incoming level IRQ lines
10 - Most onchip peripherals are wired directly to an L1 input
12 - A separate instance of the register set for each CPU, allowing individual
15 - Contains one or more enable/status word pairs per CPU
17 - No atomic set/clear operations
19 - No polarity/level/edge settings
21 - No FIFO or priority encoder logic; software is expected to read all
22 2-4 status words to determine which IRQs are pending
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Dbrcm,bcm3380-l2-intc.txt1 Broadcom BCM3380-style Level 1 / Level 2 interrupt controller
3 This interrupt controller shows up in various forms on many BCM338x/BCM63xx
6 - outputs a single interrupt signal to its interrupt controller parent
8 - contains one or more enable/status word pairs, which often appear at
11 - no atomic set/clear operations
15 - compatible: should be "brcm,bcm3380-l2-intc"
16 - reg: specifies one or more enable/status pairs, in the following format:
18 - interrupt-controller: identifies the node as an interrupt controller
19 - #interrupt-cells: specifies the number of cells needed to encode an interrupt
21 - interrupts: specifies the interrupt line in the interrupt-parent controller
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Dabilis,tb10x-ictl.txt1 TB10x Top Level Interrupt Controller
4 The Abilis TB10x SOC contains a custom interrupt controller. It performs
5 one-to-one mapping of external interrupt sources to CPU interrupts and
9 -------------------
11 - compatible: Should be "abilis,tb10x-ictl"
12 - reg: specifies physical base address and size of register range.
13 - interrupt-congroller: Identifies the node as an interrupt controller.
14 - #interrupt cells: Specifies the number of cells used to encode an interrupt
16 - interrupts: Specifies the list of interrupt lines which are handled by
17 the interrupt controller in the parent controller's notation. Interrupts
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Dbrcm,bcm7120-l2-intc.txt1 Broadcom BCM7120-style Level 2 interrupt controller
3 This interrupt controller hardware is a second level interrupt controller that
4 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
7 Such an interrupt controller has the following hardware design:
9 - outputs multiple interrupts signals towards its interrupt controller parent
11 - controls how some of the interrupts will be flowing, whether they will
12 directly output an interrupt signal towards the interrupt controller parent,
13 or if they will output an interrupt signal at this 2nd level interrupt
16 - has one 32-bit enable word and one 32-bit status word
18 - no atomic set/clear operations
[all …]
Dbrcm,bcm7038-l1-intc.txt1 Broadcom BCM7038-style Level 1 interrupt controller
3 This block is a first level interrupt controller that is typically connected
4 directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
9 - 64, 96, 128, or 160 incoming level IRQ lines
11 - Most onchip peripherals are wired directly to an L1 input
13 - A separate instance of the register set for each CPU, allowing individual
16 - Atomic mask/unmask operations
18 - No polarity/level/edge settings
20 - No FIFO or priority encoder logic; software is expected to read all
21 2-5 status words to determine which IRQs are pending
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Dst,spear3xx-shirq.txt4 of devices. The multiplexor provides a single interrupt to parent
5 interrupt controller (VIC) on behalf of a group of devices.
14 interrupt multiplexor (one node for all groups). A group in the
15 interrupt controller shares config/control registers with other groups.
16 For example, a 32-bit interrupt enable/disable config register can
17 accommodate up to 4 interrupt groups.
20 - compatible: should be, either of
21 - "st,spear300-shirq"
22 - "st,spear310-shirq"
23 - "st,spear320-shirq"
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Damazon,al-fic.txt1 Amazon's Annapurna Labs Fabric Interrupt Controller
5 - compatible: should be "amazon,al-fic"
6 - reg: physical base address and size of the registers
7 - interrupt-controller: identifies the node as an interrupt controller
8 - #interrupt-cells : must be 2. Specifies the number of cells needed to encode
9 an interrupt source. Supported trigger types are low-to-high edge
10 triggered and active high level-sensitive.
11 - interrupts: describes which input line in the interrupt parent, this
12 fic's output is connected to. This field property depends on the parent's
16 Interrupt Controllers bindings used by client devices.
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Dsamsung,exynos4210-combiner.txt1 * Samsung Exynos Interrupt Combiner Controller
3 Samsung's Exynos4 architecture includes a interrupt combiner controller which
4 can combine interrupt sources as a group and provide a single interrupt request
5 for the group. The interrupt request from each group are connected to a parent
6 interrupt controller, such as GIC in case of Exynos4210.
8 The interrupt combiner controller consists of multiple combiners. Up to eight
9 interrupt sources can be connected to a combiner. The combiner outputs one
10 combined interrupt for its eight interrupt sources. The combined interrupt
11 is usually connected to a parent interrupt controller.
13 A single node in the device tree is used to describe the interrupt combiner
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Dhisilicon,mbigen-v2.txt4 Mbigen means: message based interrupt generator.
6 MBI is kind of msi interrupt only used on Non-PCI devices.
8 To reduce the wired interrupt number connected to GIC,
9 Hisilicon designed mbigen to collect and generate interrupt.
12 Non-pci devices can connect to mbigen and generate the
13 interrupt by writing ITS register.
18 -------------------------------------------
19 - compatible: Should be "hisilicon,mbigen-v2"
21 - reg: Specifies the base physical address and size of the Mbigen
25 ------------------------------------------
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Dti,c64x+megamod-pic.txt1 C6X Interrupt Chips
2 -------------------
4 * C64X+ Core Interrupt Controller
6 The core interrupt controller provides 16 prioritized interrupts to the
8 Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
12 --------------------
13 - compatible: Should be "ti,c64x+core-pic";
14 - #interrupt-cells: <1>
16 Interrupt Specifier Definition
17 ------------------------------
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Dnxp,lpc3220-mic.txt1 * NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers
4 - compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
5 - reg: should contain IC registers location and length.
6 - interrupt-controller: identifies the node as an interrupt controller.
7 - #interrupt-cells: the number of cells to define an interrupt, should be 2.
10 IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
11 IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
12 IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
13 IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
17 - interrupts: empty for MIC interrupt controller, cascaded MIC
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Dtechnologic,ts4800.txt1 TS-4800 FPGA interrupt controller
3 TS-4800 FPGA has an internal interrupt controller. When one of the
5 parent interrupt source.
8 - compatible: should be "technologic,ts4800-irqc"
9 - interrupt-controller: identifies the node as an interrupt controller
10 - reg: physical base address of the controller and length of memory mapped
12 - #interrupt-cells: specifies the number of cells needed to encode an interrupt
14 - interrupts: specifies the interrupt line in the interrupt-parent controller
/Documentation/devicetree/bindings/pci/
Daltera-pcie.txt4 - compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0"
5 - reg: a list of physical base address and length for TXS and CRA.
6 For "altr,pcie-root-port-2.0", additional HIP base address and length.
7 - reg-names: must include the following entries:
10 "Hip": Hard IP region (if "altr,pcie-root-port-2.0")
11 - interrupts: specifies the interrupt source of the parent interrupt
12 controller. The format of the interrupt specifier depends
13 on the parent interrupt controller.
14 - device_type: must be "pci"
15 - #address-cells: set to <3>
[all …]
Daltera-pcie-msi.txt4 - compatible: should contain "altr,msi-1.0"
5 - reg: specifies the physical base address of the controller and
7 - reg-names: must include the following entries:
10 - interrupts: specifies the interrupt source of the parent interrupt
11 controller. The format of the interrupt specifier depends on the
12 parent interrupt controller.
13 - num-vectors: number of vectors, range 1 to 32.
14 - msi-controller: indicates that this is MSI controller node
19 compatible = "altr,msi-1.0";
22 reg-names = "csr", "vector_slave";
[all …]
Dxilinx-nwl-pcie.txt4 - compatible: Should contain "xlnx,nwl-pcie-2.11"
5 - #address-cells: Address representation for root ports, set to <3>
6 - #size-cells: Size representation for root ports, set to <2>
7 - #interrupt-cells: specifies the number of cells needed to encode an
8 interrupt source. The value must be 1.
9 - reg: Should contain Bridge, PCIe Controller registers location,
11 - reg-names: Must include the following entries:
15 - device_type: must be "pci"
16 - interrupts: Should contain NWL PCIe interrupt
17 - interrupt-names: Must include the following entries:
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/Documentation/devicetree/bindings/net/dsa/
Drealtek-smi.txt1 Realtek SMI-based Switches
4 The SMI "Simple Management Interface" is a two-wire protocol using
5 bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does
7 SMI-based Realtek devices.
11 - compatible: must be exactly one of:
22 - mdc-gpios: GPIO line for the MDC clock line.
23 - mdio-gpios: GPIO line for the MDIO data line.
24 - reset-gpios: GPIO line for the reset signal.
27 - realtek,disable-leds: if the LED drivers are not used in the
33 - interrupt-controller
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/Documentation/devicetree/bindings/net/
Dmdio-mux.txt8 - #address-cells = <1>;
9 - #size-cells = <0>;
12 - mdio-parent-bus : phandle to the parent MDIO bus.
14 - Other properties specific to the multiplexer/switch hardware.
17 - #address-cells = <1>;
18 - #size-cells = <0>;
19 - reg : The sub-bus number.
24 /* The parent MDIO bus. */
26 compatible = "cavium,octeon-3860-mdio";
27 #address-cells = <1>;
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Dmdio-mux-gpio.txt8 - compatible : mdio-mux-gpio.
9 - gpios : GPIO specifiers for each GPIO line. One or more must be specified.
14 /* The parent MDIO bus. */
16 compatible = "cavium,octeon-3860-mdio";
17 #address-cells = <1>;
18 #size-cells = <0>;
23 An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
27 mdio-mux {
28 compatible = "mdio-mux-gpio";
30 mdio-parent-bus = <&smi1>;
[all …]
/Documentation/devicetree/bindings/serial/
Dlantiq_asc.txt4 - compatible : Should be "lantiq,asc"
5 - reg : Address and length of the register set for the device
6 - interrupts: the 3 (tx rx err) interrupt numbers. The interrupt specifier
7 depends on the interrupt-parent interrupt controller.
10 - clocks: Should contain frequency clock and gate clock
11 - clock-names: Should be "freq" and "asc"
18 interrupt-parent = <&gic>;
23 clock-names = "freq", "asc";
29 interrupt-parent = <&icu0>;
/Documentation/devicetree/bindings/gpio/
Dgpio-xgene-sb.txt1 APM X-Gene Standby GPIO controller bindings
3 This is a gpio controller in the standby domain. It also supports interrupt in
4 some particular pins which are sourced to its parent interrupt controller
6 +-----------------+
7 | X-Gene standby |
8 | GPIO controller +------ GPIO_0
9 +------------+ | | ...
10 | Parent IRQ | EXT_INT_0 | +------ GPIO_8/EXT_INT_0
12 | (GICv2) +--------------+ +------ GPIO_[N+8]/EXT_INT_N
14 | | EXT_INT_N | +------ GPIO_[N+9]
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Dmediatek,mt7621-gpio.txt10 - #gpio-cells : Should be two. The first cell is the GPIO pin number and the
11 second cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>.
13 - #interrupt-cells : Specifies the number of cells needed to encode an
14 interrupt. Should be 2. The first cell defines the interrupt number,
16 Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
17 - compatible:
18 - "mediatek,mt7621-gpio" for Mediatek controllers
19 - reg : Physical base address and length of the controller's registers
20 - interrupt-parent : phandle of the parent interrupt controller.
21 - interrupts : Interrupt specifier for the controllers interrupt.
[all …]

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