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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | ti,c64x+megamod-pic.txt | 1 C6X Interrupt Chips
4 * C64X+ Core Interrupt Controller
6 The core interrupt controller provides 16 prioritized interrupts to the
8 Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
14 - #interrupt-cells: <1>
16 Interrupt Specifier Definition
18 Single cell specifying the core interrupt priority level (4-15) where
23 core_pic: interrupt-controller@0 {
24 interrupt-controller;
25 #interrupt-cells = <1>;
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| D | samsung,exynos4210-combiner.txt | 1 * Samsung Exynos Interrupt Combiner Controller
3 Samsung's Exynos4 architecture includes a interrupt combiner controller which
4 can combine interrupt sources as a group and provide a single interrupt request
5 for the group. The interrupt request from each group are connected to a parent
6 interrupt controller, such as GIC in case of Exynos4210.
8 The interrupt combiner controller consists of multiple combiners. Up to eight
9 interrupt sources can be connected to a combiner. The combiner outputs one
10 combined interrupt for its eight interrupt sources. The combined interrupt
11 is usually connected to a parent interrupt controller.
13 A single node in the device tree is used to describe the interrupt combiner
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| D | marvell,orion-intc.txt | 1 Marvell Orion SoC interrupt controllers
3 * Main interrupt controller
7 - reg: base address(es) of interrupt registers starting with CAUSE register
8 - interrupt-controller: identifies the node as an interrupt controller
9 - #interrupt-cells: number of cells to encode an interrupt source, shall be 1
11 The interrupt sources map to the corresponding bits in the interrupt
18 intc: interrupt-controller {
20 interrupt-controller;
21 #interrupt-cells = <1>;
26 * Bridge interrupt controller
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| D | snps,dw-apb-ictl.txt | 1 Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
3 Synopsys DesignWare provides interrupt controller IP for APB known as
4 dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
5 APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
12 - interrupt-controller: identifies the node as an interrupt controller
13 - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
15 Additional required property when it's used as secondary interrupt controller:
16 - interrupts: interrupt reference to primary interrupt controller
18 The interrupt sources map to the corresponding bits in the interrupt
27 /* dw_apb_ictl is used as secondary interrupt controller */
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| D | marvell,icu.txt | 1 Marvell ICU Interrupt Controller
4 The Marvell ICU (Interrupt Consolidation Unit) controller is
5 responsible for collecting all wired-interrupt sources in the CP and
6 communicating them to the GIC in the AP, the unit translates interrupt
17 Subnodes: Each group of interrupt is declared as a subnode of the ICU,
28 - #interrupt-cells: Specifies the number of cells needed to encode an
29 interrupt source. The value shall be 2.
31 The 1st cell is the index of the interrupt in the ICU unit.
33 The 2nd cell is the type of the interrupt. See arm,gic.txt for
36 - interrupt-controller: Identifies the node as an interrupt
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| D | interrupts.txt | 1 Specifying interrupt information for devices
4 1) Interrupt client nodes
11 properties contain a list of interrupt specifiers, one per output interrupt. The
12 format of the interrupt specifier is determined by the interrupt controller to
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
20 interrupts are routed and contains a single phandle referring to the interrupt
22 interrupt client node or in any of its parent nodes. Interrupts listed in the
23 "interrupts" property are always in reference to the node's interrupt parent.
26 to reference multiple interrupt parents or a different interrupt parent than
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| D | sigma,smp8642-intc.txt | 1 Sigma Designs SMP86xx/SMP87xx secondary interrupt controller
7 - interrupt-controller: boolean
13 - interrupt-controller: boolean
14 - #interrupt-cells: should be <2>, interrupt index and flags per interrupts.txt
15 - interrupts: interrupt spec of primary interrupt controller
19 interrupt-controller@6e000 {
23 interrupt-parent = <&gic>;
24 interrupt-controller;
28 irq0: interrupt-controller@0 {
30 interrupt-controller;
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| D | qca,ath79-misc-intc.txt | 1 Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller
3 The MISC interrupt controller is a secondary controller for lower priority
4 interrupt.
10 - interrupts: Interrupt specifier for the controllers interrupt.
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
19 Interrupt Controllers bindings used by client devices.
23 interrupt-controller@18060010 {
27 interrupt-parent = <&cpuintc>;
30 interrupt-controller;
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| D | loongson,liointc.yaml | 4 $id: "http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#"
7 title: Loongson Local I/O Interrupt Controller
13 This interrupt controller is found in the Loongson-3 family of chips as the primary
14 package interrupt controller which can route local I/O interrupt to interrupt lines
18 - $ref: /schemas/interrupt-controller.yaml#
29 interrupt-controller: true
33 Interrupt source of the CPU interrupts.
37 interrupt-names:
47 '#interrupt-cells':
53 interrupt lines. Each cell refers to a parent interrupt line from 0 to 3
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| D | nxp,lpc3220-mic.txt | 1 * NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers
6 - interrupt-controller: identifies the node as an interrupt controller.
7 - #interrupt-cells: the number of cells to define an interrupt, should be 2.
17 - interrupts: empty for MIC interrupt controller, cascaded MIC
22 /* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */
23 mic: interrupt-controller@40008000 {
26 interrupt-controller;
27 #interrupt-cells = <2>;
30 sic1: interrupt-controller@4000c000 {
33 interrupt-controller;
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| D | intel,ixp4xx-interrupt.yaml | 5 $id: "http://devicetree.org/schemas/interrupt-controller/intel,ixp4xx-interrupt.yaml#"
8 title: Intel IXP4xx XScale Networking Processors Interrupt Controller
14 This interrupt controller is found in the Intel IXP4xx processors.
19 The distinct IXP4xx families with different interrupt controller
28 - intel,ixp42x-interrupt
29 - intel,ixp43x-interrupt
30 - intel,ixp45x-interrupt
31 - intel,ixp46x-interrupt
36 interrupt-controller: true
38 '#interrupt-cells':
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| D | brcm,bcm2835-armctrl-ic.txt | 1 BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
3 The BCM2835 contains a custom top-level interrupt controller, which supports
4 72 interrupt sources using a 2-level register scheme. The interrupt
8 The BCM2836 contains the same interrupt controller with the same
9 interrupts, but the per-CPU interrupt controller is the root, and an
10 interrupt there indicates that the ARMCTRL has an interrupt to handle.
17 - interrupt-controller : Identifies the node as an interrupt controller
18 - #interrupt-cells : Specifies the number of cells needed to encode an
19 interrupt source. The value shall be 2.
21 The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
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| D | arm,vic.txt | 1 * ARM Vectored Interrupt Controller
3 One or more Vectored Interrupt Controllers (VIC's) can be connected in an ARM
4 system for interrupt routing. For multiple controllers they can either be
12 - interrupt-controller : Identifies the node as an interrupt controller
13 - #interrupt-cells : The number of cells to define the interrupts. Must be 1 as
14 the VIC has no configuration options for interrupt sources. The cell is a u32
15 and defines the interrupt number.
20 - interrupts : Interrupt source for parent controllers if the VIC is nested.
21 - valid-mask : A one cell big bit mask of valid interrupt sources. Each bit
22 represents single interrupt source, starting from source 0 at LSb and ending
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| D | snps,archs-idu-intc.txt | 1 * ARC-HS Interrupt Distribution Unit
3 This optional 2nd level interrupt controller can be used in SMP configurations
10 - interrupt-controller: This is an interrupt controller.
11 - #interrupt-cells: Must be <1> or <2>.
14 Number N of the particular interrupt line of IDU corresponds to the line N+24
15 of the core interrupt controller.
23 When no second cell is specified, the interrupt is assumed to be level
26 The interrupt controller is accessed via the special ARC AUX register
30 core_intc: core-interrupt-controller {
32 interrupt-controller;
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| D | abilis,tb10x-ictl.txt | 1 TB10x Top Level Interrupt Controller
4 The Abilis TB10x SOC contains a custom interrupt controller. It performs
5 one-to-one mapping of external interrupt sources to CPU interrupts and
13 - interrupt-congroller: Identifies the node as an interrupt controller.
14 - #interrupt cells: Specifies the number of cells used to encode an interrupt
16 - interrupts: Specifies the list of interrupt lines which are handled by
17 the interrupt controller in the parent controller's notation. Interrupts
23 intc: interrupt-controller { /* Parent interrupt controller */
24 interrupt-controller;
25 #interrupt-cells = <1>; /* For example below */
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| D | img,pdc-intc.txt | 1 * ImgTec Powerdown Controller (PDC) Interrupt Controller Binding
4 representation of a PDC IRQ controller. This has a number of input interrupt
5 lines which can wake the system, and are passed on through output interrupt
10 - compatible: Specifies the compatibility list for the interrupt controller.
16 - interrupt-controller: The presence of this property identifies the node
17 as an interrupt controller. No property value shall be defined.
19 - #interrupt-cells: Specifies the number of cells needed to encode an
20 interrupt source. The type shall be a <u32> and the value shall be 2.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
27 shared SysWake interrupt, and remaining specifies shall be PDC peripheral
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| D | brcm,bcm7120-l2-intc.txt | 1 Broadcom BCM7120-style Level 2 interrupt controller
3 This interrupt controller hardware is a second level interrupt controller that
4 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
7 Such an interrupt controller has the following hardware design:
9 - outputs multiple interrupts signals towards its interrupt controller parent
12 directly output an interrupt signal towards the interrupt controller parent,
13 or if they will output an interrupt signal at this 2nd level interrupt
20 - not all bits within the interrupt controller actually map to an interrupt
24 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
26 0 -----[ MUX ] ------------|==========> GIC interrupt 75
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| D | riscv,cpu-intc.txt | 1 RISC-V Hart-Level Interrupt Controller (HLIC)
7 Every interrupt is ultimately routed through a hart's HLIC before it
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
11 attached to every HLIC: software interrupts, the timer interrupt, and external
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
19 required to have a HLIC with these three interrupt sources present. Since the
20 interrupt map is defined by the ISA it's not listed in the HLIC's device tree
21 entry, though external interrupt controllers (like the PLIC, for example) will
23 a PLIC interrupt property will typically list the HLICs for all present HARTs
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic.txt | 2 Freescale MPIC Interrupt Controller Node
6 The Freescale MPIC interrupt controller is found on all PowerQUICC
9 additional cells in the interrupt specifier defining interrupt type
29 - interrupt-controller
32 Definition: Specifies that this node is an interrupt
35 - #interrupt-cells
38 Definition: Shall be 2 or 4. A value of 2 means that interrupt
39 specifiers do not contain the interrupt-type or type-specific
52 the boot program has initialized all interrupt source
57 that any initialization related to interrupt sources shall
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| /Documentation/devicetree/bindings/arm/freescale/ |
| D | fsl,vf610-mscm-ir.txt | 1 Freescale Vybrid Miscellaneous System Control - Interrupt Router
4 block of registers which control the interrupt router. The interrupt router
5 allows to configure the recipient of each peripheral interrupt. Furthermore
12 - reg: the register range of the MSCM Interrupt Router
15 - interrupt-controller: Identifies the node as an interrupt controller
16 - #interrupt-cells: Two cells, interrupt number and cells.
17 The hardware interrupt number according to interrupt
18 assignment of the interrupt router is required.
23 mscm_ir: interrupt-controller@40001800 {
27 interrupt-controller;
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| /Documentation/devicetree/bindings/pci/ |
| D | xilinx-pcie.txt | 6 - #interrupt-cells: specifies the number of cells needed to encode an
7 interrupt source. The value must be 1.
11 - interrupts: Should contain AXI PCIe interrupt
12 - interrupt-map-mask,
13 interrupt-map: standard PCI properties to define the mapping of the
14 PCI interface to interrupt numbers.
23 Interrupt controller child node
26 - interrupt-controller: identifies the node as an interrupt controller
29 - #interrupt-cells: specifies the number of cells needed to encode an
30 interrupt source. The value must be 1.
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| D | xilinx-nwl-pcie.txt | 7 - #interrupt-cells: specifies the number of cells needed to encode an
8 interrupt source. The value must be 1.
16 - interrupts: Should contain NWL PCIe interrupt
17 - interrupt-names: Must include the following entries:
18 "msi1, msi0": interrupt asserted when an MSI is received
19 "intx": interrupt asserted when a legacy interrupt is received
20 "misc": interrupt asserted when miscellaneous interrupt is received
21 - interrupt-map-mask and interrupt-map: standard PCI properties to define the
22 mapping of the PCI interface to interrupt numbers.
29 - legacy-interrupt-controller: Interrupt controller device node for Legacy
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| D | uniphier-pcie.txt | 24 - interrupts: A list of interrupt specifiers. According to the
25 interrupt-names, appropriate interrupts are required.
26 - interrupt-names: Must include the following entries:
27 "dma" - DMA interrupt
28 "msi" - MSI interrupt
36 - legacy-interrupt-controller: Specifies interrupt controller for legacy PCI
39 Required properties for legacy-interrupt-controller:
40 - interrupt-controller: identifies the node as an interrupt controller.
41 - #interrupt-cells: specifies the number of cells needed to encode an
42 interrupt source. The value must be 1.
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| /Documentation/devicetree/bindings/net/wireless/ |
| D | qcom,ath11k.yaml | 29 - description: misc-pulse1 interrupt events
30 - description: misc-latch interrupt events
31 - description: sw exception interrupt events
32 - description: watchdog interrupt events
33 - description: interrupt event for ring CE0
34 - description: interrupt event for ring CE1
35 - description: interrupt event for ring CE2
36 - description: interrupt event for ring CE3
37 - description: interrupt event for ring CE4
38 - description: interrupt event for ring CE5
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| /Documentation/devicetree/bindings/spmi/ |
| D | qcom,spmi-pmic-arb.txt | 7 The PMIC Arbiter can also act as an interrupt controller, providing interrupts
13 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
14 generic interrupt controller binding documentation.
20 "intr" - interrupt controller registers
32 - interrupts : interrupt list for the PMIC Arb controller, must contain a
33 single interrupt entry for the peripheral interrupt
34 - interrupt-names : corresponding interrupt names for the interrupts
36 "periph_irq" - summary interrupt for PMIC peripherals
37 - interrupt-controller : boolean indicator that the PMIC arbiter is an interrupt controller
38 - #interrupt-cells : must be set to 4. Interrupts are specified as a 4-tuple:
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