Searched full:lane (Results 1 – 25 of 63) sorted by relevance
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | st,st-mipid02.txt | 6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7 input port is a single lane 800Mbps. Both ports support clock and data lane
8 polarity swap. First port also supports data lane swap.
37 - data-lanes: shall be <1> for Port 1. for Port 0 dual-lane operation shall be
38 <1 2> or <2 1>. For Port 0 single-lane operation shall be <1> or <2>.
40 - lane-polarities: any lane can be inverted or not.
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| D | ov2680.txt | 22 - clock-lanes: should be set to <0> (clock lane on hardware lane 0).
23 - data-lanes: should be set to <1> (one CSI-2 lane supported).
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| D | imx219.yaml | 56 The sensor supports either two-lane, or four-lane operation.
57 If this property is omitted four-lane operation is assumed.
58 For two-lane operation the property must be set to <1 2>.
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| D | tc358743.txt | 16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
23 is half of the bps per lane due to DDR transmission.
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| D | ov8856.yaml | 19 serial data output (up to 4-lane).
74 The driver only supports four-lane operation.
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| /Documentation/devicetree/bindings/phy/ |
| D | phy-cadence-sierra.txt | 29 Each group of PHY lanes with a single master lane should be represented as
30 a sub-node. Note that the actual configuration of each lane is determined by
35 - reg: The master lane number. This is the lowest numbered lane
36 in the lane group.
38 master lane of the sub-node.
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| D | phy-mvebu-comphy.txt | 20 * Lane 1 (PCIe/GbE)
21 * Lane 0 (USB3/GbE)
22 * Lane 2 (SATA/USB3)
35 A sub-node is required for each comphy lane provided by the comphy.
39 - reg: COMPHY lane number.
41 input port to use for a given comphy lane.
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| D | phy-armada38x-comphy.txt | 22 A sub-node is required for each comphy lane provided by the comphy.
26 - reg: comphy lane number.
28 input port to use for a given comphy lane.
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| D | phy-cadence-torrent.yaml | 71 Each group of PHY lanes with a single master lane should be represented as a sub-node.
75 The master lane number. This is the lowest numbered lane in the lane group.
83 Contains list of resets, one per lane, to get all the link lanes out of reset.
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| D | ti,phy-j721e-wiz.yaml | 62 GPIO to signal Type-C cable orientation for lane swap.
63 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
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| /Documentation/devicetree/bindings/media/ |
| D | qcom,camss.txt | 126 Definition: The physical clock lane index. On 8916
128 clock lane is lane 1. On 8996 the value must
131 D-PHY physical clock lane is labeled as 7.
137 lane number, while the value of an entry
138 indicates physical lane index. Lane swapping
139 is supported. Physical lane indexes for
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| D | video-interfaces.txt | 489 - data-lanes: an array of physical data lane indexes. Position of an entry
490 determines the logical lane number, while the value of an entry indicates
491 physical lane, e.g. for 2-lane MIPI CSI-2 bus we could have
492 "data-lanes = <1 2>;", assuming the clock lane is on hardware lane 0.
493 If the hardware does not support lane reordering, monotonically
495 whether or not there is also a clock lane. This property is valid for
497 - clock-lanes: an array of physical clock lane indexes. Position of an entry
498 determines the logical lane number, while the value of an entry indicates
499 physical lane, e.g. for a MIPI CSI-2 bus we could have "clock-lanes = <0>;",
500 which places the clock lane on hardware lane 0. This property is valid for
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| D | ti,omap3isp.txt | 48 lane-polarities : lane polarity (required on CSI-2)
52 clock-lanes : the clock lane (from 1 to 3). (required on CSI-2)
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| /Documentation/devicetree/bindings/pci/ |
| D | mvebu-pci.txt | 77 - marvell,pcie-lane: the physical PCIe lane number, for ports having
143 marvell,pcie-lane = <0>;
163 marvell,pcie-lane = <1>;
179 marvell,pcie-lane = <2>;
195 marvell,pcie-lane = <3>;
211 marvell,pcie-lane = <0>;
227 marvell,pcie-lane = <1>;
243 marvell,pcie-lane = <2>;
259 marvell,pcie-lane = <3>;
275 marvell,pcie-lane = <0>;
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| D | cdns-pcie.yaml | 15 One per lane if more than one in the list. If only one PHY listed it must
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | ps8622.txt | 10 - lane-count: number of DP lanes to use
23 lane-count = <1>;
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| D | ti,sn65dsi86.yaml | 132 If you have 1 logical lane the bridge supports routing
162 lane-polarities:
172 lane-polarities: [data-lanes]
287 lane-polarities = <0 1 0 1>;
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| D | ps8640.yaml | 17 plus clock, at a transmission rate up to 1.5Gbit/sec per lane. The
19 3.24Gbit/sec per lane.
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| D | toshiba,tc358775.yaml | 15 MIPI DSI-RX Data 4-lane, CLK 1-lane with data rates up to 800 Mbps/lane.
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| /Documentation/driver-api/nvdimm/ |
| D | btt.rst | 163 A lane number is obtained at the start of any IO, and is used for indexing into
196 free[lane] = map[premap_aba]
199 Both threads can update their respective free[lane] with the same old, freed
213 through all the entries, and for each lane, of the set of two possible
229 2. Get a lane (and take lane_lock)
231 4. Enter post-map ABA into RTT[lane]
235 8. Remove post-map ABA entry from RTT[lane]
236 9. Release lane (and lane_lock)
241 2. Get a lane (and take lane_lock)
242 3. Use lane to index into in-memory free list and obtain a new block, next flog
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| /Documentation/devicetree/bindings/display/msm/ |
| D | dsi.txt | 59 index n describes what physical lane is mapped to the logical lane n
60 (DATAn, where n lies between 0 and 3). The clock lane position is fixed
68 The above mapping describes that the logical data lane DATA0 is mapped to
69 the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2
97 PHY lane base address. See below for each PHY revision.
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | arm,pl172.txt | 56 - mpmc,byte-lane-low: Set byte lane state to low.
109 mpmc,byte-lane-low;
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| /Documentation/devicetree/bindings/ata/ |
| D | sata_highbank.yaml | 49 phandle-combophy and lane assignment, which maps each SATA port to a
50 combophy and a lane within that combophy
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | nvidia,tegra124-xusb-padctl.txt | 33 Lane muxing:
54 - nvidia,lanes: An array of strings. Each string is the name of a lane.
60 - nvidia,iddq: Enables IDDQ mode of the lane. (0: no, 1: yes)
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| /Documentation/driver-api/media/ |
| D | csi2.rst | 54 - Two bits are transferred per clock cycle per lane.
61 on should the transmitter activate the clock on the clock lane and
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