Searched full:lanes (Results 1 – 25 of 93) sorted by relevance
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| /Documentation/devicetree/bindings/phy/ |
| D | phy-cadence-sierra.txt | 22 the clock to the lanes. "phy_clk" is deprecated.
29 Each group of PHY lanes with a single master lane should be represented as
42 - cdns,num-lanes: Number of lanes in this group. From 1 to 4. The
43 group is made up of consecutive lanes.
45 configuration of lanes.
60 cdns,num-lanes = <2>;
67 cdns,num-lanes = <1>;
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| D | nvidia,tegra124-xusb-padctl.txt | 4 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
7 documentation. Each such "pad" may control either one or multiple lanes,
8 and thus contains any logic common to all its lanes. Each lane can be
11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
15 ports (e.g. PCIe) and the lanes.
80 the pad and any of its lanes, this property must be set to "okay".
127 Each pad node has a child named "lanes" that contains one or more children of
128 its own, each representing one of the lanes controlled by the pad.
283 lanes {
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| D | phy-cadence-torrent.yaml | 71 Each group of PHY lanes with a single master lane should be represented as a sub-node.
83 Contains list of resets, one per lane, to get all the link lanes out of reset.
90 Specifies the type of PHY for which the group of PHY lanes is used.
96 cdns,num-lanes:
98 Number of lanes.
124 - cdns,num-lanes
166 cdns,num-lanes = <4>;
194 cdns,num-lanes = <2>;
203 cdns,num-lanes = <1>;
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| /Documentation/devicetree/bindings/media/xilinx/ |
| D | xlnx,csi2rxss.yaml | 88 xlnx,en-active-lanes:
91 Present if the number of active lanes can be re-configured at
92 runtime in the Protocol Configuration Register. Otherwise all lanes,
118 data-lanes:
124 1 2 - For 2 lanes enabled in IP.
125 1 2 3 - For 3 lanes enabled in IP.
126 1 2 3 4 - For 4 lanes enabled in IP.
136 - data-lanes
207 xlnx,en-active-lanes;
222 data-lanes = <1 2 3 4>;
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| /Documentation/devicetree/bindings/media/ |
| D | ti,cal.yaml | 97 clock-lanes:
100 data-lanes:
124 clock-lanes:
127 data-lanes:
173 clock-lanes = <0>;
174 data-lanes = <1 2>;
195 clock-lanes = <0>;
196 data-lanes = <1 2>;
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| D | samsung-mipi-csis.txt | 13 - bus-width : maximum number of data lanes supported (SoC specific);
42 - data-lanes : (required) an array specifying active physical MIPI-CSI2
43 data input lanes and their mapping to logical lanes; the
77 data-lanes = <1>, <2>;
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| D | renesas,csi2.yaml | 69 clock-lanes:
72 data-lanes:
78 - clock-lanes
79 - data-lanes
153 clock-lanes = <0>;
154 data-lanes = <1>;
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| D | imx7-mipi-csi2.txt | 48 - data-lanes : (required) an array specifying active physical MIPI-CSI2
49 data input lanes and their mapping to logical lanes; this
79 data-lanes = <1>;
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| D | samsung-s5k5baf.txt | 34 - data-lanes : (optional) specifies MIPI CSI-2 data lanes as covered in
55 data-lanes = <1>;
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| D | qcom,camss.txt | 123 - clock-lanes:
132 - data-lanes:
135 Definition: An array of physical data lanes indexes.
223 clock-lanes = <1>;
224 data-lanes = <0 2>;
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | adv748x.txt | 52 endpoint. Each of those endpoints shall contain the data-lanes property as
56 - data-lanes: an array of physical data lane indexes
58 sources are described. For TXA 1, 2 or 4 data lanes can be described
101 clock-lanes = <0>;
102 data-lanes = <1 2 3 4>;
111 clock-lanes = <0>;
112 data-lanes = <1>;
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| D | ov2680.txt | 22 - clock-lanes: should be set to <0> (clock lane on hardware lane 0).
23 - data-lanes: should be set to <1> (one CSI-2 lane supported).
41 clock-lanes = <0>;
42 data-lanes = <1>;
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| D | tc358743.txt | 16 - data-lanes: should be <1 2 3 4> for four-lane operation,
18 - clock-lanes: should be <0>
42 data-lanes = <1 2 3 4>;
43 clock-lanes = <0>;
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| D | ov5640.txt | 29 - clock-lanes: should be set to <0> (clock lane on hardware lane 0)
30 - data-lanes: should be set to <1> or <1 2> (one or two CSI-2 lanes supported)
64 clock-lanes = <0>;
65 data-lanes = <1 2>;
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| D | sony,imx214.txt | 6 Image data is sent through MIPI CSI-2, through 2 or 4 lanes at a maximum
30 - data-lanes: check ../video-interfaces.txt
48 data-lanes = <1 2 3 4>;
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| /Documentation/devicetree/bindings/display/panel/ |
| D | raydium,rm67191.yaml | 25 dsi-lanes:
26 description: Number of DSI lanes to be used must be <3> or <4>
45 - dsi-lanes
62 dsi-lanes = <4>;
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| D | lvds.yaml | 52 [VESA] specifications. Data are transferred as follows on 3 LVDS lanes.
63 specifications. Data are transferred as follows on 4 LVDS lanes.
75 Data are transferred as follows on 4 LVDS lanes.
97 data lanes, transmitting bits for slots 6 to 0 instead of 0 to 6.
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | nvidia,tegra124-xusb-padctl.txt | 10 The Tegra XUSB pad controller manages a set of lanes, each of which can be
40 Each subnode describes groups of lanes along with parameters and pads that
54 - nvidia,lanes: An array of strings. Each string is the name of a lane.
62 Note that not all of these properties are valid for all lanes. Lanes can be
117 nvidia,lanes = "pcie-0", "pcie-1";
123 nvidia,lanes = "pcie-2", "pcie-3",
130 nvidia,lanes = "sata-0";
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| /Documentation/devicetree/bindings/pci/ |
| D | nvidia,tegra20-pcie.txt | 104 - If lanes 0 to 3 are used:
107 - If lanes 4 or 5 are used:
148 - nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
150 - Root port 0 uses 4 lanes, root port 1 is unused.
151 - Both root ports use 2 lanes.
157 number of lanes in the nvidia,num-lanes property. Entries are of the form
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
210 nvidia,num-lanes = <2>;
224 nvidia,num-lanes = <2>;
316 nvidia,num-lanes = <2>;
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| D | rockchip-pcie-ep.txt | 29 - phy-names: Must include 4 entries for all 4 lanes even if some of
37 - num-lanes: number of lanes to use
50 num-lanes = <4>;
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| D | pci-armada8k.txt | 23 PCIe lanes.
24 - phy-names: names of the PHYs corresponding to the number of lanes.
46 num-lanes = <1>;
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| D | designware-pcie.txt | 28 - num-lanes: number of lanes to use (this property should be specified unless
65 num-lanes = <1>;
76 num-lanes = <1>;
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| D | pci-ep.yaml | 30 num-lanes:
31 description: maximum number of lanes
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| /Documentation/devicetree/bindings/display/ti/ |
| D | ti,omap5-dss.txt | 77 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
99 - lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
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| D | ti,omap4-dss.txt | 96 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
118 - lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
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