Searched +full:low +full:- +full:power +full:- +full:enable (Results 1 – 25 of 141) sorted by relevance
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| /Documentation/devicetree/bindings/usb/ |
| D | pxa-usb.txt | 6 - compatible: Should be "marvell,pxa-ohci" for USB controllers
10 - "marvell,enable-port1", "marvell,enable-port2", "marvell,enable-port3"
12 - "marvell,port-mode" selects the mode of the ports:
16 - "marvell,power-sense-low" - power sense pin is low-active.
17 - "marvell,power-control-low" - power control pin is low-active.
18 - "marvell,no-oc-protection" - disable over-current protection.
19 - "marvell,oc-mode-perport" - enable per-port over-current protection.
20 - "marvell,power_on_delay" Power On to Power Good time - in ms.
25 compatible = "marvell,pxa-ohci", "usb-ohci";
28 marvell,enable-port1;
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | pincfg-node.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pincfg-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
21 bias-disable:
25 bias-high-impedance:
27 description: high impedance mode ("third-state", "floating")
29 bias-bus-hold:
33 bias-pull-up:
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| D | pinctrl-single.txt | 1 One-register-per-pin type device tree based pinctrl driver
4 - compatible : "pinctrl-single" or "pinconf-single".
5 "pinctrl-single" means that pinconf isn't supported.
6 "pinconf-single" means that generic pinconf is supported.
8 - reg : offset and length of the register set for the mux registers
10 - #pinctrl-cells : number of cells in addition to the index, set to 1
11 for pinctrl-single,pins and 2 for pinctrl-single,bits
13 - pinctrl-single,register-width : pinmux register access width in bits
15 - pinctrl-single,function-mask : mask of allowed pinmux function bits
19 - pinctrl-single,function-off : function off mode for disabled state if
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| /Documentation/devicetree/bindings/iio/frequency/ |
| D | adf4350.txt | 4 - compatible: Should be one of
7 - reg: SPI chip select numbert for the device
8 - spi-max-frequency: Max SPI frequency to use (< 20000000)
9 - clocks: From common clock binding. Clock is phandle to clock for
13 - gpios: GPIO Lock detect - If set with a valid phandle and GPIO number,
15 - adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
16 - adi,power-up-frequency: If set in Hz the PLL tunes to
18 - adi,reference-div-factor: If set the driver skips dynamic calculation
20 - adi,reference-doubler-enable: Enables reference doubler.
21 - adi,reference-div2-enable: Enables reference divider.
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| /Documentation/devicetree/bindings/mfd/ |
| D | max77620.txt | 1 MAX77620 Power management IC from Maxim Semiconductor.
4 -------------------
5 - compatible: Must be one of
9 - reg: I2C device address.
12 -------------------
13 - interrupts: The interrupt on the parent the controller is
15 - interrupt-controller: Marks the device node as an interrupt controller.
16 - #interrupt-cells: is <2> and their usage is compliant to the 2 cells
17 variant of <../interrupt-controller/interrupts.txt>
19 are defined at dt-bindings/mfd/max77620.h.
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| D | as3722.txt | 1 * ams AS3722 Power management IC.
4 -------------------
5 - compatible: Must be "ams,as3722".
6 - reg: I2C device address.
7 - interrupt-controller: AS3722 has internal interrupt controller which takes the
8 interrupt request from internal sub-blocks like RTC, regulators, GPIOs as well
10 - #interrupt-cells: Should be set to 2 for IRQ number and flags.
12 of AS3722 are defined at dt-bindings/mfd/as3722.h
14 interrupts.txt, using dt-bindings/irq.
17 --------------------
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| D | twl6040.txt | 3 The TWL6040s are 8-channel high quality low-power audio codecs providing audio,
9 - compatible : "ti,twl6040" for twl6040, "ti,twl6041" for twl6041
10 - reg: must be 0x4b for i2c address
11 - interrupts: twl6040 has one interrupt line connecteded to the main SoC
12 - gpio-controller:
13 - #gpio-cells = <1>: twl6040 provides GPO lines.
14 - #clock-cells = <0>; twl6040 is a provider of pdmclk which is used by McPDM
15 - twl6040,audpwron-gpio: Power on GPIO line for the twl6040
17 - vio-supply: Regulator for the twl6040 VIO supply
18 - v2v1-supply: Regulator for the twl6040 V2V1 supply
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| /Documentation/devicetree/bindings/display/panel/ |
| D | panel-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
24 width-mm:
29 height-mm:
43 non-descriptive information. For instance an LCD panel in a system that
55 panel-timing:
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| /Documentation/devicetree/bindings/power/supply/ |
| D | max8903-charger.txt | 4 - compatible: "maxim,max8903" for MAX8903 Battery Charger
5 - dok-gpios: Valid DC power has been detected (active low, input), optional if uok-gpios is provided
6 - uok-gpios: Valid USB power has been detected (active low, input), optional if dok-gpios is provid…
9 - cen-gpios: Charge enable pin (active low, output)
10 - chg-gpios: Charger status pin (active low, input)
11 - flt-gpios: Fault pin (active low, output)
12 - dcm-gpios: Current limit mode setting (DC=1 or USB=0, output)
13 - usus-gpios: USB suspend pin (active high, output)
18 max8903-charger {
20 dok-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
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| D | summit,smb347-charger.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/power/supply/summit,smb347-charger.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - David Heidelberg <david@ixit.cz>
11 - Dmitry Osipenko <digetx@gmail.com>
16 - summit,smb345
17 - summit,smb347
18 - summit,smb358
26 monitored-battery:
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| D | bq2515x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/power/supply/bq2515x.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI bq2515x 500-mA Linear charger family
11 - Dan Murphy <dmurphy@ti.com>
12 - Ricardo Rivera-Matos <r-rivera-matos@ti.com>
18 push-button controller.
27 - ti,bq25150
28 - ti,bq25155
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| /Documentation/devicetree/bindings/input/ |
| D | iqs269a.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS269A is an 8-channel capacitive touch controller that features
14 additional Hall-effect and inductive sensing capabilities.
28 "#address-cells":
31 "#size-cells":
34 azoteq,hall-enable:
37 Enables Hall-effect sensing on channels 6 and 7. In this case, keycodes
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| /Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra186-pmc.txt | 1 NVIDIA Tegra Power Management Controller (PMC)
4 - compatible: Should contain one of the following:
5 - "nvidia,tegra186-pmc": for Tegra186
6 - "nvidia,tegra194-pmc": for Tegra194
7 - "nvidia,tegra234-pmc": for Tegra234
8 - reg: Must contain an (offset, length) pair of the register set for each
9 entry in reg-names.
10 - reg-names: Must include the following entries:
11 - "pmc"
12 - "wake"
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| /Documentation/admin-guide/pm/ |
| D | intel-speed-select.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 With Intel(R) SST, one server can be configured for power and performance for a
14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic…
15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
19 dynamically without pre-configuring via BIOS setup options. This dynamic
25 how these commands change the power and performance profile of the system under
29 intel-speed-select configuration tool
32 Most Linux distribution packages may include the "intel-speed-select" tool. If not,
38 # cd tools/power/x86/intel-speed-select/
43 ------------
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| /Documentation/arm/pxa/ |
| D | mfp.rst | 7 MFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and
15 mechanism is introduced from PXA3xx to completely move the pin-mux functions
16 out of the GPIO controller. In addition to pin-mux configurations, the MFP
17 also controls the low power state, driving strength, pull-up/down and event
21 +--------+
22 | |--(GPIO19)--+
24 | |--(GPIO...) |
25 +--------+ |
26 | +---------+
27 +--------+ +------>| |
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| /Documentation/devicetree/bindings/rtc/ |
| D | rtc-omap.txt | 4 - compatible:
5 - "ti,da830-rtc" - for RTC IP used similar to that on DA8xx SoC family.
6 - "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family.
7 This RTC IP has special WAKE-EN Register to enable
11 - "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family.
12 - reg: Address range of rtc register set
13 - interrupts: rtc timer, alarm interrupts in order
16 - system-power-controller: whether the rtc is controlling the system power
18 - clocks: Any internal or external clocks feeding in to rtc
19 - clock-names: Corresponding names of the clocks
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| D | abracon,abx80x.txt | 1 Abracon ABX80X I2C ultra low power RTC/Alarm chip
9 - "compatible": should one of:
20 Using "abracon,abx80x" will enable chip autodetection.
21 - "reg": I2C bus address of the device
27 and valid to enable charging:
29 - "abracon,tc-diode": should be "standard" (0.6V) or "schottky" (0.3V)
30 - "abracon,tc-resistor": should be <0>, <3>, <6> or <11>. 0 disables the output
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| D | rtc-palmas.txt | 4 - compatible:
5 - "ti,palmas-rtc" for palma series of the RTC controller
6 - interrupts: Interrupt number of RTC submodule on device.
10 - ti,backup-battery-chargeable: The Palmas series device like TPS65913 or
12 battery is removed or in very low power state. The backup battery
13 can be chargeable or non-chargeable. This flag will tells whether
15 enable the charging.
16 - ti,backup-battery-charge-high-current: Enable high current charging in
25 compatible = "ti,palmas-rtc";
26 interrupt-parent = <&palmas>;
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | aptina,mt9v111.txt | 2 ----------------------------
4 The Aptina MT9V111 is a 1/4-Inch VGA-format digital image sensor with a core
8 of image resolution and formats controllable through a simple two-wires
12 --------------------
14 - compatible: shall be "aptina,mt9v111".
15 - clocks: reference to the system clock input provider.
18 --------------------
20 - enable-gpios: output enable signal, pin name "OE#". Active low.
21 - standby-gpios: low power state control signal, pin name "STANDBY".
23 - reset-gpios: chip reset signal, pin name "RESET#". Active low.
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| /Documentation/devicetree/bindings/clock/ |
| D | lpc1850-creg-clk.txt | 4 control registers for two low speed clocks. One of the clocks is a
5 32 kHz oscillator driver with power up/down and clock gating. Next
9 The 32 kHz can also be routed to other peripherials to enable low
10 power modes.
13 Documentation/devicetree/bindings/clock/clock-bindings.txt
16 - compatible:
17 Should be "nxp,lpc1850-creg-clk"
18 - #clock-cells:
20 - clocks:
23 The creg-clk node must be a child of the creg syscon node.
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| /Documentation/devicetree/bindings/regulator/ |
| D | sprd,sc2731-regulator.txt | 3 The SC2731 integrates low-voltage and low quiescent current DCDC/LDO.
5 their own bypass (power-down) control signals. External tantalum or MLCC
9 - compatible: should be "sprd,sc27xx-regulator".
26 compatible = "sprd,sc27xx-regulator";
29 regulator-name = "vddarm0";
30 regulator-min-microvolt = <400000>;
31 regulator-max-microvolt = <1996875>;
32 regulator-ramp-delay = <25000>;
33 regulator-always-on;
37 regulator-name = "vddcama0";
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| /Documentation/w1/slaves/ |
| D | w1_therm.rst | 15 -----------
48 -1 if at least one sensor still in conversion, 1 if conversion is complete
65 ``conv_time``; 3) use ``features`` to enable poll for conversion
66 completion. Options 2, 3 can't be used in parasite power mode. To get back to
71 the sensor. Resolution is reset when the sensor gets power-cycled.
80 Some non-genuine DS18B20 chips are fixed in 12-bit mode only, so the actual
85 The write-only sysfs entry ``eeprom`` is an alternative for EEPROM operations.
89 ``ext_power`` entry allows checking the power state of each device. Reads
92 Sysfs ``alarms`` allow read or write TH and TL (Temperature High an Low) alarms.
93 Values shall be space separated and in the device range (typical -55 degC
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| /Documentation/trace/coresight/ |
| D | coresight-cpu-debug.rst | 9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
29 --------------
31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
32 registers to decide if sample-based profiling is implemented or not. On some
36 - At the time this documentation was written, the debug driver mainly relies on
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| /Documentation/driver-api/ |
| D | slimbus.rst | 9 ----------------
10 SLIMbus (Serial Low Power Interchip Media Bus) is a specification developed by
12 configuration, and is a 2-wire multi-drop implementation (clock, and data).
15 (System-on-Chip) and peripheral components (typically codec). SLIMbus uses
16 Time-Division-Multiplexing to accommodate multiple data channels, and
24 A data channel is used for data-transfer between 2 SLIMbus devices. Data
28 ---------------------
36 Framer device is responsible for clocking the bus, and transmitting frame-sync
49 responsible to select the active-framer for clocking the bus.
51 Per specification, SLIMbus uses "clock gears" to do power management based on
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| /Documentation/devicetree/bindings/display/ |
| D | ssd1307fb.txt | 4 - compatible: Should be "solomon,<chip>fb-<bus>". The only supported bus for
7 - reg: Should contain address of the controller on the I2C bus. Most likely
9 - pwm: Should contain the pwm to use according to the OF device tree PWM
11 - solomon,height: Height in pixel of the screen driven by the controller
12 - solomon,width: Width in pixel of the screen driven by the controller
13 - solomon,page-offset: Offset of pages (band of 8 pixels) that the screen is
17 - reset-gpios: The GPIO used to reset the OLED display, if available. See
19 - vbat-supply: The supply for VBAT
20 - solomon,segment-no-remap: Display needs normal (non-inverted) data column
22 - solomon,col-offset: Offset of columns (COL/SEG) that the screen is mapped to.
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