Searched full:misses (Results 1 – 25 of 29) sorted by relevance
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| /Documentation/devicetree/bindings/arc/ |
| D | archs-pct.txt | 4 CPU and cache events like cache misses and hits. Like conventional PCT there
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| D | pct.txt | 4 CPU and cache events like cache misses and hits. Like conventional PCT there
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| /Documentation/devicetree/bindings/perf/ |
| D | nds32v3-pmu.txt | 3 NDS32 core have a PMU for counting cpu and cache events like cache misses.
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-event_source-devices-events | 2 /sys/devices/cpu/events/branch-misses
4 /sys/devices/cpu/events/cache-misses
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| D | sysfs-block-bcache | 35 For backing devices: integer number of cache misses.
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| /Documentation/virt/ |
| D | guest-halt-polling.rst | 60 be increased from 10000, to avoid misses during the initial
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| /Documentation/admin-guide/device-mapper/ |
| D | cache.rst | 240 <#read hits> <#read misses> <#write hits> <#write misses>
257 #read misses Number of times a READ bio has been mapped
261 #write misses Number of times a WRITE bio has been
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| /Documentation/admin-guide/ |
| D | bcache.rst | 367 - Traffic's still going to the spindle/still getting cache misses
385 - Still getting cache misses, of the same data
388 the way cache coherency is handled for cache misses. If a btree node is full,
499 Hits and misses are counted per individual IO as bcache sees them; a
503 Hits and misses for IO that is intended to skip the cache are still counted,
509 since the synchronization for cache misses was rewritten)
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| /Documentation/staging/ |
| D | static-keys.rst | 307 5,569,188 branch-misses # 2.67% of all branches ( +- 0.54% )
324 4,884,119 branch-misses # 2.36% of all branches ( +- 0.85% )
329 'branch-misses'. This is where we would expect to get the most savings, since
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| /Documentation/devicetree/bindings/arm/ |
| D | pmu.yaml | 14 ARM cores often have a PMU for counting cpu and cache events like cache misses
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| /Documentation/hwmon/ |
| D | lm63.rst | 51 capabilities added. It misses some of the LM86 features though:
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| /Documentation/arm64/ |
| D | amu.rst | 35 misses in the last level cache within the clock domain.
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| /Documentation/admin-guide/pm/ |
| D | cpuidle.rst | 366 by the ``CPUIdle`` driver: ``hits``, ``misses`` and ``early_hits``.
368 The ``hits`` and ``misses`` metrics measure the likelihood that a given idle
379 length and the observed idle duration). In turn, the ``misses`` metric is
393 to the sleep length. Then, the ``hits`` and ``misses`` metrics of that idle
396 duration after CPU wakeup). If the ``misses`` one is greater, the governor
404 ``misses`` and ``early_hits`` metrics.]
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| /Documentation/arm/ |
| D | tcm.rst | 53 timing and cannot wait for cache misses.
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| /Documentation/core-api/ |
| D | dma-attributes.rst | 92 - You know that the penalty of TLB misses while accessing the
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| /Documentation/admin-guide/mm/ |
| D | transhuge.rst | 43 memory in turn reducing the number of TLB misses. With
409 from reduced TLB misses.
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| D | concepts.rst | 75 TLB misses.
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| /Documentation/RCU/ |
| D | rculist_nulls.rst | 63 And note the traditional hlist_for_each_entry_rcu() misses this smp_rmb()::
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| /Documentation/vm/ |
| D | numa.rst | 43 [cache misses] to be to "local" memory--memory on the same cell, if any--or
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| /Documentation/x86/ |
| D | resctrl_ui.rst | 577 hits and misses.
594 residency (cache hits and misses) measurement captured in the
598 residency (cache hits and misses) measurement captured in the
638 Example of cache hits/misses debugging
642 and misses using the platform's precision counters.
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| D | pti.rst | 93 TLB misses after a context switch. The actual loss of
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| /Documentation/process/ |
| D | 1.Intro.rst | 223 more development after its release. This argument misses the value of
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| /Documentation/timers/ |
| D | no_hz.rst | 302 and TLB misses can be reduced (and in some cases eliminated) by
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| /Documentation/virt/kvm/ |
| D | timekeeping.rst | 432 inactive, the P-state may be raised temporarily to service cache misses from
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| /Documentation/driver-api/ |
| D | uio-howto.rst | 342 loss of data if your userspace program misses an interrupt.
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