Searched +full:multi +full:- +full:channel (Results 1 – 25 of 84) sorted by relevance
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| /Documentation/devicetree/bindings/sound/ |
| D | sprd-mcdt.txt | 1 Spreadtrum Multi-Channel Data Transfer Binding
3 The Multi-channel data transfer controller is used for sound stream
5 supports 10 DAC channel and 10 ADC channel, and each channel can be
9 - compatible: Should be "sprd,sc9860-mcdt".
10 - reg: Should contain registers address and length.
11 - interrupts: Should contain one interrupt shared by all channel.
16 compatible = "sprd,sc9860-mcdt";
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| D | mchp-i2s-mcc.txt | 1 * Microchip I2S Multi-Channel Controller
4 - compatible: Should be "microchip,sam9x60-i2smcc".
5 - reg: Should be the physical base address of the controller and the
7 - interrupts: Should contain the interrupt for the controller.
8 - dmas: Should be one per channel name listed in the dma-names property,
9 as described in atmel-dma.txt and dma.txt files.
10 - dma-names: Identifier string for each DMA request line in the dmas property.
12 - clocks: Must contain an entry for each entry in clock-names.
13 Please refer to clock-bindings.txt.
14 - clock-names: Should be one of each entry matching the clocks phandles list:
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| D | davinci-mcbsp.txt | 4 This binding describes the "Multi-channel Buffered Serial Port" (McBSP)
5 audio interface found in some TI DaVinci processors like the OMAP-L138 or AM180x.
10 - compatible :
11 "ti,da850-mcbsp" : for DA850, AM180x and OPAM-L138 platforms
13 - reg : physical base address and length of the controller memory mapped
15 - reg-names : Should contain:
19 - dmas: three element list of DMA controller phandles, DMA request line and
20 TC channel ordered triplets.
21 - dma-names: identifier string for each DMA request line in the dmas property.
27 - interrupts : Interrupt numbers for McBSP
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| /Documentation/sound/hd-audio/ |
| D | controls.rst | 2 HD-Audio Codec-Specific Mixer Controls
6 This file explains the codec-specific mixer controls.
9 --------------
11 Channel Mode
12 This is an enum control to change the surround-channel setup,
16 jack-retasking of multi-I/O jacks.
18 Auto-Mute Mode
19 This is an enum control to change the auto-mute behavior of the
20 headphone and line-out jacks. If built-in speakers and headphone
21 and/or line-out jacks are available on a machine, this controls
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| /Documentation/devicetree/bindings/timer/ |
| D | renesas,mtu2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Multi-Function Timer Pulse Unit 2 (MTU2)
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 The MTU2 is a multi-purpose, multi-channel timer/counter with configurable clock inputs
23 - enum:
24 - renesas,mtu2-r7s72100 # RZ/A1H
25 - const: renesas,mtu2
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| D | andestech,atcpit100-timer.txt | 2 ------------------------------------------------------------------
6 This timer is a set of compact multi-function timers, which can be
9 It supports up to 4 PIT channels. Each PIT channel is a
10 multi-function timer and provide the following usage scenarios:
11 One 32-bit timer
12 Two 16-bit timers
13 Four 8-bit timers
14 One 16-bit PWM
15 One 16-bit timer and one 8-bit PWM
16 Two 8-bit timer and one 8-bit PWM
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | keystone-navigator-qmss.txt | 5 multi-core Navigator. QMSS consist of queue managers, packed-data structure
9 management of the packet queues. Packets are queued/de-queued by writing or
20 - compatible : Must be "ti,keystone-navigator-qmss".
21 : Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
22 - clocks : phandle to the reference clock for this device.
23 - queue-range : <start number> total range of queue numbers for the device.
24 - linkram0 : <address size> for internal link ram, where size is the total
26 - linkram1 : <address size> for external link ram, where size is the total
29 - qmgrs : child node describing the individual queue managers on the
32 -- managed-queues : the actual queues managed by each queue manager
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| /Documentation/sound/cards/ |
| D | cmipci.rst | 2 Brief Notes on C-Media 8338/8738/8768/8770 Driver
8 Front/Rear Multi-channel Playback
9 ---------------------------------
13 DACs, both streams are handled independently unlike the 4/6ch multi-
14 channel playbacks in the section below.
22 - The first DAC supports U8 and S16LE formats, while the second DAC
24 - The second DAC supports only two channel stereo.
30 The rear output can be heard only when "Four Channel Mode" switch is
35 When "Four Channel Mode" switch is off, the output from rear speakers
43 front one) and was so excited. It was even with "Four Channel" bit
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| /Documentation/devicetree/bindings/dma/ |
| D | snps,dma-spear1340.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 - $ref: "dma-controller.yaml#"
18 const: snps,dma-spear1340
20 "#dma-cells":
26 for transfers on dynamically allocated channel. Fourth cell is the
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| D | img-mdc-dma.txt | 1 * IMG Multi-threaded DMA Controller (MDC)
4 - compatible: Must be "img,pistachio-mdc-dma".
5 - reg: Must contain the base address and length of the MDC registers.
6 - interrupts: Must contain all the per-channel DMA interrupts.
7 - clocks: Must contain an entry for each entry in clock-names.
8 See ../clock/clock-bindings.txt for details.
9 - clock-names: Must include the following entries:
10 - sys: MDC system interface clock.
11 - img,cr-periph: Must contain a phandle to the peripheral control syscon
12 node which contains the DMA request to channel mapping registers.
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| D | ste-dma40.txt | 4 - compatible: "stericsson,dma40"
5 - reg: Address range of the DMAC registers
6 - reg-names: Names of the above areas to use during resource look-up
7 - interrupt: Should contain the DMAC interrupt number
8 - #dma-cells: must be <3>
9 - memcpy-channels: Channels to be used for memcpy
12 - dma-channels: Number of channels supported by hardware - if not present
14 - disabled-channels: Channels which can not be used
18 dma: dma-controller@801c0000 {
19 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
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| /Documentation/fb/ |
| D | viafb.rst | 6 --------
15 ---------------
34 ----------------------
47 - 640x480 (default)
48 - 720x480
49 - 800x600
50 - 1024x768
53 - 8, 16, 32 (default:32)
56 - 60, 75, 85, 100, 120 (default:60)
59 - 0 : expansion (default)
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| /Documentation/devicetree/bindings/iio/dac/ |
| D | ad5755.txt | 1 * Analog Devices AD5755 IIO Multi-Channel DAC Linux Driver
4 - compatible: Has to contain one of the following:
6 adi,ad5755-1
11 - reg: spi chip select number for the device
12 - spi-cpha or spi-cpol: is the only modes that is supported
15 - spi-max-frequency: Definition as per
16 Documentation/devicetree/bindings/spi/spi-bus.txt
19 See include/dt-bindings/iio/ad5755.h
20 - adi,ext-dc-dc-compenstation-resistor: boolean set if the hardware have an
23 - adi,dc-dc-phase:
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| /Documentation/mips/ |
| D | ingenic-tcu.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
11 - JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
14 - JZ4725B introduced a separate channel, called Operating System Timer
15 (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is
16 64-bit.
18 - Each one of the TCU channels has its own clock, which can be reparented to three
21 - The watchdog and OST hardware blocks also feature a TCSR register with the same
23 - The TCU registers used to gate/ungate can also gate/ungate the watchdog and
26 - Each TCU channel works in one of two modes:
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| /Documentation/driver-api/dmaengine/ |
| D | dmatest.rst | 11 capability of the following: DMA_MEMCPY (memory-to-memory), DMA_MEMSET
12 (const-to-memory or memory-to-memory, when emulated), DMA_XOR, DMA_PQ.
18 Part 1 - How to build the test module
23 Device Drivers -> DMA Engine support -> DMA Test client
28 Part 2 - When dmatest is built as a module
33 % modprobe dmatest timeout=2000 iterations=1 channel=dma0chan0 run=1
40 % echo dma0chan0 > /sys/module/dmatest/parameters/channel
45 dmatest.timeout=2000 dmatest.iterations=1 dmatest.channel=dma0chan0 dmatest.run=1
47 Example of multi-channel test usage (new in the 5.0 kernel)::
52 % echo dma0chan0 > /sys/module/dmatest/parameters/channel
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| /Documentation/gpu/ |
| D | mcde.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 drm/mcde ST-Ericsson MCDE Multi-channel display engine
7 .. kernel-doc:: drivers/gpu/drm/mcde/mcde_drv.c
8 :doc: ST-Ericsson MCDE Driver
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| /Documentation/devicetree/bindings/leds/ |
| D | leds-lp50xx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/leds-lp50xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dan Murphy <dmurphy@ti.com>
13 The LP50XX is multi-channel, I2C RGB LED Drivers that can group RGB LEDs into
27 - ti,lp5009
28 - ti,lp5012
29 - ti,lp5018
30 - ti,lp5024
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| D | leds-lp55xx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/leds-lp55xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacek Anaszewski <jacek.anaszewski@gmail.com>
11 - Pavel Machek <pavel@ucw.cz>
14 Bindings for the TI/National Semiconductor LP55xx and LP8501 multi channel
27 - national,lp5521
28 - national,lp5523
29 - ti,lp55231
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| /Documentation/devicetree/bindings/mmc/ |
| D | renesas,mmcif.txt | 1 * Renesas Multi Media Card Interface (MMCIF) Controller
9 - compatible: should be "renesas,mmcif-<soctype>", "renesas,sh-mmcif" as a
11 - "renesas,mmcif-r7s72100" for the MMCIF found in r7s72100 SoCs
12 - "renesas,mmcif-r8a73a4" for the MMCIF found in r8a73a4 SoCs
13 - "renesas,mmcif-r8a7740" for the MMCIF found in r8a7740 SoCs
14 - "renesas,mmcif-r8a7742" for the MMCIF found in r8a7742 SoCs
15 - "renesas,mmcif-r8a7743" for the MMCIF found in r8a7743 SoCs
16 - "renesas,mmcif-r8a7744" for the MMCIF found in r8a7744 SoCs
17 - "renesas,mmcif-r8a7745" for the MMCIF found in r8a7745 SoCs
18 - "renesas,mmcif-r8a7778" for the MMCIF found in r8a7778 SoCs
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| /Documentation/devicetree/bindings/thermal/ |
| D | exynos-thermal.txt | 5 - compatible : One of the following:
6 "samsung,exynos3250-tmu"
7 "samsung,exynos4412-tmu"
8 "samsung,exynos4210-tmu"
9 "samsung,exynos5250-tmu"
10 "samsung,exynos5260-tmu"
11 "samsung,exynos5420-tmu" for TMU channel 0, 1 on Exynos5420
12 "samsung,exynos5420-tmu-ext-triminfo" for TMU channels 2, 3 and 4
14 "samsung,exynos5433-tmu"
15 "samsung,exynos7-tmu"
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-sprd-adi.txt | 3 ADI is the abbreviation of Anolog-Digital interface, which is used to access
12 which means we can just link one analog chip address to one hardware channel,
13 then users can access the mapped analog chip address by this hardware channel
16 Thus we introduce one property named "sprd,hw-channels" to configure hardware
17 channels, the first value specifies the hardware channel id which is used to
21 Since we have multi-subsystems will use unique ADI to access analog chip, when
34 - compatible: Should be "sprd,sc9860-adi".
35 - reg: Offset and length of ADI-SPI controller register space.
36 - #address-cells: Number of cells required to define a chip select address
37 on the ADI-SPI bus. Should be set to 1.
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| /Documentation/devicetree/bindings/pwm/ |
| D | kontron,sl28cpld-pwm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/kontron,sl28cpld-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Walle <michael@walle.cc>
13 This module is part of the sl28cpld multi-function device. For more
16 The controller supports one PWM channel and supports only four distinct
20 - $ref: pwm.yaml#
24 const: kontron,sl28cpld-pwm
29 "#pwm-cells":
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| /Documentation/devicetree/bindings/mfd/ |
| D | max77802.txt | 1 Maxim MAX77802 multi-function device
4 efficiency Buck regulators, 32 Low-DropOut (LDO) regulators used to power
5 up application processors and peripherals, a 2-channel 32kHz clock outputs,
6 a Real-Time-Clock (RTC) and a I2C interface to program the individual
9 Bindings for the built-in 32k clock generator block and
14 - compatible : Must be "maxim,max77802"
15 - reg : Specifies the I2C slave address of PMIC block.
16 - interrupts : I2C device IRQ line connected to the main SoC.
22 interrupt-parent = <&intc>;
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| /Documentation/devicetree/bindings/hwmon/ |
| D | max31785.txt | 8 The Maxim MAX31785 is a PMBus device providing closed-loop, multi-channel fan
14 - compatible : One of "maxim,max31785" or "maxim,max31785a"
15 - reg : I2C address, one of 0x52, 0x53, 0x54, 0x55.
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| /Documentation/hwmon/ |
| D | max197.rst | 14 Datasheet: http://datasheets.maxim-ic.com/en/ds/MAX197.pdf
20 Datasheet: http://datasheets.maxim-ic.com/en/ds/MAX199.pdf
23 -----------
25 The A/D converters MAX197, and MAX199 are both 8-Channel, Multi-Range, 5V,
26 12-Bit DAS with 8+4 Bus Interface and Fault Protection.
28 The available ranges for the MAX197 are {0,-5V} to 5V, and {0,-10V} to 10V,
29 while they are {0,-2V} to 2V, and {0,-4V} to 4V on the MAX199.
32 -------------
40 On success, the function must return the 12-bit raw value read from the chip,
47 7,6 PD1,PD0 Clock and Power-Down modes
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