Home
last modified time | relevance | path

Searched full:nvidia (Results 1 – 25 of 133) sorted by relevance

123456

/Documentation/devicetree/bindings/arm/
Dtegra.yaml7 title: NVIDIA Tegra device tree bindings
11 - Jonathan Hunter <jonathanh@nvidia.com>
22 - nvidia,harmony
23 - nvidia,seaboard
24 - nvidia,ventana
25 - const: nvidia,tegra20
32 - const: nvidia,tegra20
38 - const: nvidia,tegra20
41 - const: nvidia,tegra20
44 - nvidia,beaver
[all …]
Dnvidia,tegra194-ccplex.yaml4 $id: "http://devicetree.org/schemas/arm/nvidia,tegra194-ccplex.yaml#"
7 title: NVIDIA Tegra194 CPU Complex device tree bindings
11 - Jonathan Hunter <jonathanh@nvidia.com>
12 - Sumit Gupta <sumitg@nvidia.com>
25 - nvidia,tegra194-ccplex
27 nvidia,bpmp:
38 compatible = "nvidia,tegra194-ccplex";
39 nvidia,bpmp = <&bpmp>;
44 compatible = "nvidia,tegra194-carmel";
51 compatible = "nvidia,tegra194-carmel";
[all …]
/Documentation/devicetree/bindings/clock/
Dnvidia,tegra124-dfll.txt1 NVIDIA Tegra124 DFLL FCPU clocksource
14 - "nvidia,tegra124-dfll": for Tegra124
15 - "nvidia,tegra210-dfll": for Tegra210
39 - nvidia,sample-rate: Sample rate of the DFLL control loop.
40 - nvidia,droop-ctrl: See the register CL_DVFS_DROOP_CTRL in the TRM.
41 - nvidia,force-mode: See the field DFLL_PARAMS_FORCE_MODE in the TRM.
42 - nvidia,cf: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM.
43 - nvidia,ci: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM.
44 - nvidia,cg: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM.
47 - nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM.
[all …]
/Documentation/devicetree/bindings/sound/
Dnvidia,tegra-audio-wm8903.txt1 NVIDIA Tegra audio complex
4 - compatible : "nvidia,tegra-audio-wm8903"
11 - nvidia,model : The user-visible name of this sound complex.
12 - nvidia,audio-routing : A list of the connections between audio components.
23 - nvidia,i2s-controller : The phandle of the Tegra I2S1 controller
24 - nvidia,audio-codec : The phandle of the WM8903 audio codec
27 - nvidia,spkr-en-gpios : The GPIO that enables the speakers
28 - nvidia,hp-mute-gpios : The GPIO that mutes the headphones
29 - nvidia,hp-det-gpios : The GPIO that detect headphones are plugged in
30 - nvidia,int-mic-en-gpios : The GPIO that enables the internal microphone
[all …]
Dnvidia,tegra-audio-rt5677.txt1 NVIDIA Tegra audio complex, with RT5677 CODEC
4 - compatible : "nvidia,tegra-audio-rt5677"
11 - nvidia,model : The user-visible name of this sound complex.
12 - nvidia,audio-routing : A list of the connections between audio components.
24 - nvidia,i2s-controller : The phandle of the Tegra I2S controller that's
26 - nvidia,audio-codec : The phandle of the RT5677 audio codec. This binding
30 - nvidia,hp-det-gpios : The GPIO that detects headphones are plugged in
31 - nvidia,hp-en-gpios : The GPIO that enables headphone amplifier
32 - nvidia,mic-present-gpios: The GPIO that mic jack is plugged in
33 - nvidia,dmic-clk-en-gpios : The GPIO that gates DMIC clock signal
[all …]
Dnvidia,tegra-audio-max98090.txt1 NVIDIA Tegra audio complex, with MAX98090 CODEC
4 - compatible : "nvidia,tegra-audio-max98090"
11 - nvidia,model : The user-visible name of this sound complex.
12 - nvidia,audio-routing : A list of the connections between audio components.
23 - nvidia,i2s-controller : The phandle of the Tegra I2S controller that's
25 - nvidia,audio-codec : The phandle of the MAX98090 audio codec.
28 - nvidia,hp-det-gpios : The GPIO that detect headphones are plugged in
29 - nvidia,mic-det-gpios : The GPIO that detect microphones are plugged in
34 compatible = "nvidia,tegra-audio-max98090-venice2",
35 "nvidia,tegra-audio-max98090";
[all …]
Dnvidia,tegra-audio-rt5640.txt1 NVIDIA Tegra audio complex, with RT5640 CODEC
4 - compatible : "nvidia,tegra-audio-rt5640"
11 - nvidia,model : The user-visible name of this sound complex.
12 - nvidia,audio-routing : A list of the connections between audio components.
22 - nvidia,i2s-controller : The phandle of the Tegra I2S controller that's
24 - nvidia,audio-codec : The phandle of the RT5640 audio codec. This binding
28 - nvidia,hp-det-gpios : The GPIO that detects headphones are plugged in
33 compatible = "nvidia,tegra-audio-rt5640-dalmore",
34 "nvidia,tegra-audio-rt5640";
35 nvidia,model = "NVIDIA Tegra Dalmore";
[all …]
Dnvidia,tegra-audio-wm8753.txt1 NVIDIA Tegra audio complex
4 - compatible : "nvidia,tegra-audio-wm8753"
11 - nvidia,model : The user-visible name of this sound complex.
12 - nvidia,audio-routing : A list of the connections between audio components.
21 - nvidia,i2s-controller : The phandle of the Tegra I2S1 controller
22 - nvidia,audio-codec : The phandle of the WM8753 audio codec
26 compatible = "nvidia,tegra-audio-wm8753-whistler",
27 "nvidia,tegra-audio-wm8753"
28 nvidia,model = "tegra-wm8753-harmony";
30 nvidia,audio-routing =
[all …]
Dnvidia,tegra-audio-alc5632.txt1 NVIDIA Tegra audio complex
4 - compatible : "nvidia,tegra-audio-alc5632"
11 - nvidia,model : The user-visible name of this sound complex.
12 - nvidia,audio-routing : A list of the connections between audio components.
23 - nvidia,i2s-controller : The phandle of the Tegra I2S controller
24 - nvidia,audio-codec : The phandle of the ALC5632 audio codec
29 compatible = "nvidia,tegra-audio-alc5632-paz00",
30 "nvidia,tegra-audio-alc5632";
32 nvidia,model = "Compal PAZ00";
34 nvidia,audio-routing =
[all …]
Dnvidia,tegra-audio-sgtl5000.txt1 NVIDIA Tegra audio complex, with SGTL5000 CODEC
4 - compatible : "nvidia,tegra-audio-sgtl5000"
11 - nvidia,model : The user-visible name of this sound complex.
12 - nvidia,audio-routing : A list of the connections between audio components.
22 - nvidia,i2s-controller : The phandle of the Tegra I2S controller that's
24 - nvidia,audio-codec : The phandle of the SGTL5000 audio codec.
30 "nvidia,tegra-audio-sgtl5000";
31 nvidia,model = "Toradex Apalis T30";
32 nvidia,audio-routing =
36 nvidia,i2s-controller = <&tegra_i2s2>;
[all …]
/Documentation/devicetree/bindings/pinctrl/
Dnvidia,tegra114-pinmux.txt1 NVIDIA Tegra114 pinmux controller
4 pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
5 nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
9 - compatible: "nvidia,tegra114-pinmux"
16 - nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
17 - nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
18 - nvidia,lock: Integer. Lock the pin configuration against further changes
20 - nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
21 - nvidia,rcv-sel: Integer. Select VIL/VIH receivers. 0: normal, 1: high.
22 - nvidia,drive-type: Integer. Valid range 0...3.
[all …]
Dnvidia,tegra124-pinmux.txt1 NVIDIA Tegra124 pinmux controller
4 pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
5 nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
9 - compatible: For Tegra124, must contain "nvidia,tegra124-pinmux". For
10 Tegra132, must contain '"nvidia,tegra132-pinmux", "nvidia-tegra124-pinmux"'.
19 - nvidia,enable-input: Integer. Enable the pin's input path.
22 - nvidia,open-drain: Integer.
25 - nvidia,lock: Integer. Lock the pin configuration against further changes
29 - nvidia,io-reset: Integer. Reset the IO path.
32 - nvidia,rcv-sel: Integer. Select VIL/VIH receivers.
[all …]
Dnvidia,tegra194-pinmux.txt1 NVIDIA Tegra194 pinmux controller
4 - compatible: "nvidia,tegra194-pinmux"
24 - nvidia,pins : An array of strings. Each string contains the name of a pin or
28 - nvidia,function: A string containing the name of the function to mux to the
30 - nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
32 - nvidia,tristate: Integer.
34 - nvidia,enable-input: Integer. Enable the pin's input path.
37 - nvidia,open-drain: Integer.
40 - nvidia,lock: Integer. Lock the pin configuration against further changes
44 - nvidia,io-hv: Integer. Select high-voltage receivers.
[all …]
Dnvidia,tegra30-pinmux.txt1 NVIDIA Tegra30 pinmux controller
4 as described in nvidia,tegra20-pinmux.txt. In fact, this document assumes
9 - compatible: "nvidia,tegra30-pinmux"
14 - nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
15 - nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
16 - nvidia,lock: Integer. Lock the pin configuration against further changes
18 - nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
27 These all support nvidia,function, nvidia,tristate, nvidia,pull,
28 nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,
29 nvidia,io-reset.
[all …]
Dnvidia,tegra20-pinmux.txt1 NVIDIA Tegra20 pinmux controller
4 - compatible: "nvidia,tegra20-pinmux"
31 - nvidia,pins : An array of strings. Each string contains the name of a pin or
35 - nvidia,function: A string containing the name of the function to mux to the
38 - nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
40 - nvidia,tristate: Integer.
42 - nvidia,high-speed-mode: Integer. Enable high speed mode the pins.
44 - nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
46 - nvidia,low-power-mode: Integer. Valid values 0-3. 0 is least power, 3 is
49 - nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
[all …]
/Documentation/devicetree/bindings/misc/
Dnvidia,tegra20-apbmisc.txt1 NVIDIA Tegra APBMISC block
5 - Tegra20: "nvidia,tegra20-apbmisc"
6 - Tegra30: "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"
7 - Tegra114: "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"
8 - Tegra124: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"
9 - Tegra132: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"
10 - Tegra210: "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"
17 - nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit).
/Documentation/devicetree/bindings/fuse/
Dnvidia,tegra20-fuse.txt1 NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block.
4 - compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30,
5 must contain "nvidia,tegra30-efuse". For Tegra114, must contain
6 "nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse".
7 For Tegra132 must contain "nvidia,tegra132-efuse", "nvidia,tegra124-efuse".
8 For Tegra210 must contain "nvidia,tegra210-efuse". For Tegra186 must contain
9 "nvidia,tegra186-efuse". For Tegra194 must contain "nvidia,tegra194-efuse".
10 For Tegra234 must contain "nvidia,tegra234-efuse".
12 nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
15 nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse:
[all …]
/Documentation/devicetree/bindings/mmc/
Dnvidia,tegra20-sdhci.txt1 * NVIDIA Tegra Secure Digital Host Controller
11 - "nvidia,tegra20-sdhci": for Tegra20
12 - "nvidia,tegra30-sdhci": for Tegra30
13 - "nvidia,tegra114-sdhci": for Tegra114
14 - "nvidia,tegra124-sdhci": for Tegra124 and Tegra132
15 - "nvidia,tegra210-sdhci": for Tegra210
16 - "nvidia,tegra186-sdhci": for Tegra186
17 - "nvidia,tegra194-sdhci": for Tegra194
38 compatible = "nvidia,tegra20-sdhci";
60 - nvidia,only-1-8-v : The presence of this property indicates that the
[all …]
/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-flowctrl.txt1 NVIDIA Tegra Flow Controller
5 - "nvidia,tegra20-flowctrl": for Tegra20
6 - "nvidia,tegra30-flowctrl": for Tegra30
7 - "nvidia,tegra114-flowctrl": for Tegra114
8 - "nvidia,tegra124-flowctrl": for Tegra124
9 - "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl": for Tegra132
10 - "nvidia,tegra210-flowctrl": for Tegra210
16 compatible = "nvidia,tegra20-flowctrl";
Dnvidia,tegra20-pmc.yaml4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra20-pmc
18 - nvidia,tegra30-pmc
19 - nvidia,tegra114-pmc
20 - nvidia,tegra124-pmc
21 - nvidia,tegra210-pmc
62 nvidia,invert-interrupt:
70 nvidia,core-power-req-active-high:
[all …]
/Documentation/devicetree/bindings/pwm/
Dnvidia,tegra20-pwm.txt5 - "nvidia,tegra20-pwm": for Tegra20
6 - "nvidia,tegra30-pwm", "nvidia,tegra20-pwm": for Tegra30
7 - "nvidia,tegra114-pwm", "nvidia,tegra20-pwm": for Tegra114
8 - "nvidia,tegra124-pwm", "nvidia,tegra20-pwm": for Tegra124
9 - "nvidia,tegra132-pwm", "nvidia,tegra20-pwm": for Tegra132
10 - "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210
11 - "nvidia,tegra186-pwm": for Tegra186
12 - "nvidia,tegra194-pwm": for Tegra194
39 compatible = "nvidia,tegra20-pwm";
59 nvidia,pins = "pe7";
[all …]
/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra124-emc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
7 title: NVIDIA Tegra124 SoC External Memory Controller
11 - Jon Hunter <jonathanh@nvidia.com>
19 const: nvidia,tegra124-emc
32 nvidia,memory-controller:
41 nvidia,ram-code:
57 nvidia,emc-auto-cal-config:
63 nvidia,emc-auto-cal-config2:
69 nvidia,emc-auto-cal-config3:
75 nvidia,emc-auto-cal-interval:
[all …]
/Documentation/devicetree/bindings/phy/
Dnvidia,tegra20-usb-phy.txt6 - compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy".
7 For Tegra30, must contain "nvidia,tegra30-usb-phy". Otherwise, must contain
8 "nvidia,<chip>-usb-phy" plus at least one of the above, where <chip> is
25 with pad group aka "nvidia,pins" cdev2 and pin mux option config aka
26 "nvidia,function" pllp_out4).
36 - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
39 - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before
41 - nvidia,elastic-limit : Variable FIFO Depth of elastic input store
42 - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait
44 - nvidia,term-range-adj : Range adjusment on terminations
[all …]
/Documentation/devicetree/bindings/bus/
Dnvidia,tegra20-gmi.txt1 Device tree bindings for NVIDIA Tegra Generic Memory Interface bus
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
43 - nvidia,snor-data-width-32bit: Use 32bit data-bus, default is 16bit.
44 - nvidia,snor-mux-mode: Enable address/data MUX mode.
45 - nvidia,snor-rdy-active-before-data: Assert RDY signal one cycle before data.
47 - nvidia,snor-rdy-active-high: RDY signal is active high
48 - nvidia,snor-adv-active-high: ADV signal is active high
49 - nvidia,snor-oe-active-high: WE/OE signal is active high
50 - nvidia,snor-cs-active-high: CS signal is active high
[all …]
/Documentation/devicetree/bindings/thermal/
Dnvidia,tegra124-soctherm.txt10 - compatible : For Tegra124, must contain "nvidia,tegra124-soctherm".
11 For Tegra132, must contain "nvidia,tegra132-soctherm".
12 For Tegra210, must contain "nvidia,tegra210-soctherm".
39 - nvidia,priority: Each throttles has its own throttle settings, so the
47 - nvidia,cpu-throt-percent: This property is for Tegra124 and Tegra210.
50 - nvidia,cpu-throt-level: This property is only for Tegra132, it is the
56 - nvidia,gpu-throt-level: This property is for Tegra124 and Tegra210.
71 - nvidia,count-threshold: Specifies the number of OC events that are
74 - nvidia,polarity-active-low: Configures the polarity of the OC alaram
76 - nvidia,alarm-filter: Number of clocks to filter event. When the filter
[all …]

123456