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/Documentation/devicetree/bindings/phy/
Dcdns,salvo-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright (c) 2020 NXP
4 ---
5 $id: "http://devicetree.org/schemas/phy/cdns,salvo-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Peter Chen <peter.chen@nxp.com>
16 - nxp,salvo-phy
24 clock-names:
26 - const: salvo_phy_clk
28 power-domains:
[all …]
/Documentation/devicetree/bindings/sound/
Dfsl,easrc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP Asynchronous Sample Rate Converter (ASRC) Controller
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
17 const: fsl,imx8mn-easrc
27 - description: Peripheral clock
29 clock-names:
31 - const: mem
36 dma-names:
[all …]
/Documentation/devicetree/bindings/remoteproc/
Dimx-rproc.txt1 NXP iMX6SX/iMX7D Co-Processor Bindings
2 ----------------------------------------
4 This binding provides support for ARM Cortex M4 Co-processor found on some
5 NXP iMX SoCs.
8 - compatible Should be one of:
9 "fsl,imx7d-cm4"
10 "fsl,imx6sx-cm4"
11 - clocks Clock for co-processor (See: ../clock/clock-bindings.txt)
12 - syscon Phandle to syscon block which provide access to
16 - memory-region list of phandels to the reserved memory regions.
[all …]
/Documentation/devicetree/bindings/perf/
Dfsl-imx-ddr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale(NXP) IMX8 DDR performance monitor
10 - Frank Li <frank.li@nxp.com>
15 - enum:
16 - fsl,imx8-ddr-pmu
17 - fsl,imx8m-ddr-pmu
18 - fsl,imx8mp-ddr-pmu
[all …]
/Documentation/devicetree/bindings/interrupt-controller/
Dfsl,intmux.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,intmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Joakim Zhang <qiangqing.zhang@nxp.com>
14 const: fsl,imx-intmux
26 interrupt-controller: true
28 '#interrupt-cells':
36 clock-names:
40 - compatible
[all …]
/Documentation/devicetree/bindings/net/
Dimx-dwmac.txt1 IMX8 glue layer controller, NXP imx8 families support Synopsys MAC 5.10a IP.
3 This file documents platform glue layer for IMX.
9 - compatible: Should be "nxp,imx8mp-dwmac-eqos" to select glue layer
10 and "snps,dwmac-5.10a" to select IP version.
11 - clocks: Must contain a phandle for each entry in clock-names.
12 - clock-names: Should be "stmmaceth" for the host clock.
17 - "mem" clock is required for imx8dxl platform.
18 - "mem" clock is not required for imx8mp platform.
19 - interrupt-names: Should contain a list of interrupt names corresponding to
23 - intf_mode: Should be phandle/offset pair. The phandle to the syscon node which
[all …]
/Documentation/devicetree/bindings/soc/imx/
Dfsl,aips-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,aips-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
21 const: fsl,aips-bus
23 - compatible
28 - const: fsl,aips-bus
29 - const: simple-bus
35 - compatible
[all …]
/Documentation/devicetree/bindings/display/imx/
Dnxp,imx8mq-dcss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright 2019 NXP
4 ---
5 $id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Laurentiu Palcu <laurentiu.palcu@nxp.com>
17 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
23 const: nxp,imx8mq-dcss
27 - description: DCSS base address and size, up to IRQ steer start
28 - description: DCSS BLKCTL base address and size
[all …]
/Documentation/devicetree/bindings/pwm/
Dimx-tpm-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/imx-tpm-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <anson.huang@nxp.com>
17 "#pwm-cells":
22 - fsl,imx7ulp-pwm
27 assigned-clocks:
30 assigned-clock-parents:
37 - "#pwm-cells"
[all …]
/Documentation/devicetree/bindings/nvmem/
Dimx-iim.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/imx-iim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
17 - $ref: "nvmem.yaml#"
22 - fsl,imx25-iim
23 - fsl,imx27-iim
24 - fsl,imx31-iim
25 - fsl,imx35-iim
[all …]
Dimx-ocotp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/imx-ocotp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
10 - Anson Huang <Anson.Huang@nxp.com>
13 This binding represents the on-chip eFuse OTP controller found on
18 - $ref: "nvmem.yaml#"
23 - items:
24 - enum:
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/Documentation/devicetree/bindings/clock/
Dimx8qxp-lpcg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
10 - Aisheng Dong <aisheng.dong@nxp.com>
13 The Low-Power Clock Gate (LPCG) modules contain a local programming
24 include/dt-bindings/clock/imx8-clock.h
29 - fsl,imx8qxp-lpcg-adma
30 - fsl,imx8qxp-lpcg-conn
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/Documentation/devicetree/bindings/dsp/
Dfsl,dsp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8 DSP core
10 - Daniel Baluta <daniel.baluta@nxp.com>
14 advanced pre- and post- audio processing.
19 - fsl,imx8qxp-dsp
20 - fsl,imx8qm-dsp
21 - fsl,imx8mp-dsp
28 - description: ipg clock
[all …]
/Documentation/devicetree/bindings/mfd/
Drohm,bd71847-pmic.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/rohm,bd71847-pmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
14 single-core, dual-core, and quad-core SoCs such as NXP-i.MX 8M. It is
18 …/www.rohm.com/products/power-management/power-management-ic-for-system/industrial-consumer-applica…
19 …//www.rohm.com/products/power-management/power-management-ic-for-system/industrial-consumer-applic…
24 - rohm,bd71847
25 - rohm,bd71850
[all …]
/Documentation/devicetree/bindings/i2c/
Di2c-imx-lpi2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-imx-lpi2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - enum:
19 - fsl,imx7ulp-lpi2c
20 - fsl,imx8qm-lpi2c
21 - items:
[all …]
/Documentation/devicetree/bindings/watchdog/
Dfsl-imx-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/fsl-imx-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
13 - $ref: "watchdog.yaml#"
18 - const: fsl,imx21-wdt
19 - items:
20 - enum:
21 - fsl,imx8mm-wdt
[all …]
/Documentation/devicetree/bindings/thermal/
Dimx-thermal.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/imx-thermal.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX Thermal Binding
10 - Shawn Guo <shawnguo@kernel.org>
11 - Anson Huang <Anson.Huang@nxp.com>
16 - fsl,imx6q-tempmon
17 - fsl,imx6sx-tempmon
18 - fsl,imx7d-tempmon
[all …]
/Documentation/devicetree/bindings/arm/freescale/
Dfsl,scu.txt1 NXP i.MX System Controller Firmware (SCFW)
2 --------------------------------------------------------------------
4 The System Controller Firmware (SCFW) is a low-level system function
5 which runs on a dedicated Cortex-M core to provide power, clock, and
9 The AP communicates with the SC using a multi-ported MU module found
22 -------------------
23 - compatible: should be "fsl,imx-scu".
24 - mbox-names: should include "tx0", "tx1", "tx2", "tx3",
27 - mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for
63 Client nodes are maintained as children of the relevant IMX-SCU device node.
[all …]
/Documentation/devicetree/bindings/pinctrl/
Dfsl,imx8mn-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/fsl,imx8mn-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
13 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
18 const: fsl,imx8mn-iomuxc
37 be found in <arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h>. The last
38 integer CONFIG is the pad setting value like pull-up on this pin. Please
40 $ref: /schemas/types.yaml#/definitions/uint32-matrix
[all …]
Dfsl,imx8mp-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/fsl,imx8mp-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
13 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
18 const: fsl,imx8mp-iomuxc
37 be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last
38 integer CONFIG is the pad setting value like pull-up on this pin. Please
40 $ref: /schemas/types.yaml#/definitions/uint32-matrix
[all …]
Dfsl,imx8mm-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/fsl,imx8mm-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
13 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
18 const: fsl,imx8mm-iomuxc
37 be found in <arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h>. The last
38 integer CONFIG is the pad setting value like pull-up on this pin. Please
40 $ref: /schemas/types.yaml#/definitions/uint32-matrix
[all …]
Dfsl,imx8mq-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/fsl,imx8mq-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
13 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
18 const: fsl,imx8mq-iomuxc
37 be found in <arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h>. The last
38 integer CONFIG is the pad setting value like pull-up on this pin. Please
40 $ref: /schemas/types.yaml#/definitions/uint32-matrix
[all …]
/Documentation/devicetree/bindings/gpio/
Dfsl-imx-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/gpio/fsl-imx-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
15 - enum:
16 - fsl,imx1-gpio
17 - fsl,imx21-gpio
18 - fsl,imx31-gpio
19 - fsl,imx35-gpio
[all …]
/Documentation/devicetree/bindings/serial/
Dfsl-imx-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabio Estevam <fabio.estevam@nxp.com>
13 - $ref: "serial.yaml"
14 - $ref: "rs485.yaml"
19 - const: fsl,imx1-uart
20 - const: fsl,imx21-uart
21 - items:
[all …]
/Documentation/devicetree/bindings/interconnect/
Dfsl,imx8m-noc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Leonard Crestez <leonard.crestez@nxp.com>
18 for normal (non-secure) world.
20 The buses are based on externally licensed IPs such as ARM NIC-301 and
22 interconnect IPs into imx SOCs.
27 - items:
28 - enum:
[all …]

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