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/Documentation/devicetree/bindings/net/
Ddavinci_emac.txt9 - reg: Offset and length of the register set for the device
10 - ti,davinci-ctrl-reg-offset: offset to control register
11 - ti,davinci-ctrl-mod-reg-offset: offset to control module register
12 - ti,davinci-ctrl-ram-offset: offset to control module ram
33 ti,davinci-ctrl-reg-offset = <0x3000>;
34 ti,davinci-ctrl-mod-reg-offset = <0x2000>;
35 ti,davinci-ctrl-ram-offset = <0>;
Dhisilicon-hns-dsaf.txt30 - reset-field-offset: is offset of reset field. Its value depends on the hardware
41 - cpld-syscon: is syscon handle + register offset pair for cpld register. It is
43 - port-rst-offset: is offset of reset field for each port in dsaf. Its value
45 - port-mode-offset: is offset of port mode field for each port in dsaf. Its
66 reset-field-offset = 0;
/Documentation/devicetree/bindings/reset/
Dintel,rcu-gw.yaml23 description: Global reset register offset and bit offset.
26 - description: Register offset
27 - description: Register bit offset
35 First cell is reset request register offset.
36 Second cell is bit offset in reset request register.
37 Third cell is bit offset in reset status register.
38 For LGM SoC, reset cell count is 2 as bit offset in
40 3 for legacy SoCs as bit offset differs.
Dsocfpga-reset.txt7 - altr,modrst-offset : Should contain the offset of the first modrst register.
15 altr,modrst-offset = <0x10>;
/Documentation/devicetree/bindings/mmc/
Dnvidia,tegra20-sdhci.txt62 - nvidia,pad-autocal-pull-up-offset-3v3,
63 nvidia,pad-autocal-pull-down-offset-3v3 : Specify drive strength
65 - nvidia,pad-autocal-pull-up-offset-1v8,
66 nvidia,pad-autocal-pull-down-offset-1v8 : Specify drive strength
68 - nvidia,pad-autocal-pull-up-offset-3v3-timeout,
69 nvidia,pad-autocal-pull-down-offset-3v3-timeout : Specify drive
72 - nvidia,pad-autocal-pull-up-offset-1v8-timeout,
73 nvidia,pad-autocal-pull-down-offset-1v8-timeout : Specify drive
76 - nvidia,pad-autocal-pull-up-offset-sdr104,
77 nvidia,pad-autocal-pull-down-offset-sdr104 : Specify drive strength
[all …]
/Documentation/trace/
Duprobetracer.rst19 user to calculate the offset of the probepoint in the object.
29 p[:[GRP/]EVENT] PATH:OFFSET [FETCHARGS] : Set a uprobe
30 r[:[GRP/]EVENT] PATH:OFFSET [FETCHARGS] : Set a return uprobe (uretprobe)
31 p[:[GRP/]EVENT] PATH:OFFSET%return [FETCHARGS] : Set a return uprobe (uretprobe)
36 on PATH+OFFSET.
38 OFFSET : Offset where the probe is inserted.
39 OFFSET%return : Offset where the return probe is inserted.
44 @+OFFSET : Fetch memory at OFFSET (OFFSET from same file as PATH)
72 offset, and container-size (usually 32). The syntax is::
74 b<bit-width>@<bit-offset>/<container-size>
[all …]
/Documentation/devicetree/bindings/leds/
Dregister-bit-led.txt17 - offset : register offset to the register controlling this LED
37 offset = <0x08>;
45 offset = <0x08>;
53 offset = <0x08>;
61 offset = <0x08>;
68 offset = <0x08>;
75 offset = <0x08>;
82 offset = <0x08>;
89 offset = <0x08>;
/Documentation/devicetree/bindings/arm/hisilicon/controller/
Dsysctrl.yaml19 offset. In addition, the HiP01 system controller has some specific control
54 smp-offset:
56 offset in sysctrl for notifying slave cpu booting
63 resume-offset:
64 description: offset in sysctrl for notifying cpu0 when resume
67 reboot-offset:
68 description: offset in sysctrl for system reboot
102 smp-offset = <0x31c>;
103 resume-offset = <0x308>;
104 reboot-offset = <0x4>;
[all …]
/Documentation/devicetree/bindings/mtd/
Dfsl-upm-nand.txt6 - fsl,upm-addr-offset : UPM pattern offset for the address latch.
7 - fsl,upm-cmd-offset : UPM pattern offset for the command latch.
33 fsl,upm-addr-offset = <16>;
34 fsl,upm-cmd-offset = <8>;
53 fsl,upm-addr-offset = <0x10>;
54 fsl,upm-cmd-offset = <0x08>;
/Documentation/leds/
Dleds-mlxcpld.rst28 - CPLD reg offset: 0x20
32 - CPLD reg offset: 0x20
36 - CPLD reg offset: 0x21
40 - CPLD reg offset: 0x21
44 - CPLD reg offset: 0x22
48 - CPLD reg offset: 0x22
77 - CPLD reg offset: 0x20
81 - CPLD reg offset: 0x21
85 - CPLD reg offset: 0x23
89 - CPLD reg offset: 0x23
[all …]
/Documentation/devicetree/bindings/regulator/
Danatop-regulator.yaml21 anatop-reg-offset:
23 description: u32 value representing the anatop MFD register offset.
45 anatop-delay-reg-offset:
47 description: u32 value representing the anatop MFD step time register offset.
59 description: u32 value representing regulator enable bit offset.
68 - anatop-reg-offset
85 anatop-reg-offset = <0x140>;
88 anatop-delay-reg-offset = <0x170>;
/Documentation/devicetree/bindings/clock/
Darm,syscon-icst.yaml19 an ICST clock request after a write to the 32 bit register at an offset
22 writing a special token to another offset in the system controller.
79 lock-offset:
81 description: Offset to the unlocking register for the oscillator
83 vco-offset:
85 description: Offset to the VCO register for the oscillator
99 lock-offset = <0x08>;
100 vco-offset = <0x00>;
Dxgene.txt49 - csr-offset : Offset to the CSR reset register from the reset address base.
52 - enable-offset : Offset to the enable register from the reset address base.
55 - divider-offset : Offset to the divider CSR register from the divider base.
107 divider-offset = <0x238>;
121 csr-offset = <0x0>;
123 enable-offset = <0x8>;
125 divider-offset = <0x10>;
Dti-clkctrl.txt11 the hardware offset from the clkctrl instance register space. The optional
12 clocks can be specified by clkctrl hardware offset and the index of the
25 offset from the clock domain base and the second being the
46 #define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET)
/Documentation/devicetree/bindings/power/reset/
Dsyscon-poweroff.yaml15 defined by the register map pointed by syscon reference plus the offset
27 offset:
29 description: Offset in the register map for the poweroff register (in bytes).
42 - offset
60 offset = <0x0>;
Dsyscon-reboot-mode.yaml17 parental dt-node plus the offset. So the SYSCON reboot-mode node
28 offset:
30 description: Offset in the register map for the mode register (in bytes)
41 - offset
49 offset = <0x40>;
Dsyscon-reboot.yaml15 defined by the SYSCON register map base plus the offset with the value and
30 offset:
32 description: Offset in the register map for the reboot register (in bytes).
47 - offset
65 offset = <0x0>;
/Documentation/devicetree/bindings/timer/
Dqcom,msm-timer.txt28 - cpu-offset : per-cpu offset used when the timer is accessed without the
29 CPU remapping facilities. The offset is
30 cpu-offset + (0x10000 * cpu-nr).
46 cpu-offset = <0x40000>;
/Documentation/devicetree/bindings/input/touchscreen/
Dedt-ft5x06.yaml31 offset-x: true
32 offset-y: true
68 offset:
74 offset-x:
75 description: Same as offset, but applies only to the horizontal position.
81 offset-y:
82 description: Same as offset, but applies only to the vertical position.
/Documentation/devicetree/bindings/display/
Dssd1307fb.txt13 - solomon,page-offset: Offset of pages (band of 8 pixels) that the screen is
22 - solomon,col-offset: Offset of columns (COL/SEG) that the screen is mapped to.
26 - solomon,com-offset: Number of the COM pin wired to the first display line
58 solomon,com-offset = <32>;
/Documentation/devicetree/bindings/c6x/
Ddscr.txt35 offset of the devstat register
38 offset, start bit, and bitsize of silicon revision field
41 offset and bitmask of RMII reset field. May have multiple tuples if more
46 a lock register. Each tuple consists of the register offset, lock register
50 offset and key values of two "kick" registers used to write protect other
58 a register offset and four cells representing bytes in the register from
73 reg is the offset of the register holding the control bits
90 reg is the offset of the register holding the status bits
97 Offset and default value for register used to set access privilege for
/Documentation/userspace-api/media/v4l/
Dpixfmt-sdr-pcu16be.rst18 padded with 0. I value starts first and Q value starts at an offset
19 equalling half of the buffer size (i.e.) offset = buffersize/2. Out of
30 * - Offset:
46 * - start + offset:
51 * - start + offset + 4:
Dpixfmt-sdr-pcu20be.rst18 padded with 0. I value starts first and Q value starts at an offset
19 equalling half of the buffer size (i.e.) offset = buffersize/2. Out of
30 * - Offset:
46 * - start + offset:
51 * - start + offset + 4:
/Documentation/driver-api/
Dio-mapping.rst31 unsigned long offset)
33 'offset' is the offset within the defined mapping region.
35 creation function yields undefined results. Using an offset
60 unsigned long offset)
86 map_atomic and map functions add the requested offset to the base of the
/Documentation/devicetree/bindings/sound/
Dmtk-btcvsd-snd.txt8 - mediatek,offset: Array contains of register offset and mask
23 mediatek,offset = <0xf00 0x800 0xfd0 0xfd4 0xfd8>;

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