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/Documentation/devicetree/bindings/soundwire/
Dqcom,sdw.txt7 - compatible:
10 Definition: must be "qcom,soundwire-v<MAJOR>.<MINOR>.<STEP>",
12 "qcom,soundwire-v1.3.0"
13 "qcom,soundwire-v1.5.0"
14 "qcom,soundwire-v1.5.1"
15 "qcom,soundwire-v1.6.0"
16 - reg:
18 Value type: <prop-encoded-array>
22 - interrupts:
24 Value type: <prop-encoded-array>
[all …]
/Documentation/devicetree/bindings/arm/
Dcoresight.txt11 * Required properties for all components *except* non-configurable replicators
12 and non-configurable funnels:
16 - Embedded Trace Buffer (version 1.0):
17 "arm,coresight-etb10", "arm,primecell";
19 - Trace Port Interface Unit:
20 "arm,coresight-tpiu", "arm,primecell";
22 - Trace Memory Controller, used for Embedded Trace Buffer(ETB),
26 "arm,coresight-tmc", "arm,primecell";
28 - Trace Programmable Funnel:
29 "arm,coresight-dynamic-funnel", "arm,primecell";
[all …]
Dete.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Suzuki K Poulose <suzuki.poulose@arm.com>
12 - Mathieu Poirier <mathieu.poirier@linaro.org>
19 components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer
27 pattern: "^ete([0-9a-f]+)$"
30 - const: arm,embedded-trace-extension
37 out-ports:
40 $ref: /schemas/graph.yaml#/properties/ports
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/Documentation/sound/cards/
Dserial-u16550.rst7 * 0 - Roland Soundcanvas support (default)
8 * 1 - Midiator MS-124T support (1)
9 * 2 - Midiator MS-124W S/A mode (2)
10 * 3 - MS-124W M/B mode support (3)
11 * 4 - Generic device with multiple input support (4)
13 For the Midiator MS-124W, you must set the physical M-S and A-B
17 (midiCnD0-midiCnD15). Whenever you write to a different substream, the driver
28 /sbin/modprobe snd-serial-u16550 port=0x3f8 irq=4 speed=115200
30 Usage example for Roland SoundCanvas with 4 MIDI ports:
34 /sbin/modprobe snd-serial-u16550 port=0x3f8 irq=4 outs=4
[all …]
Demu10k1-jack.rst12 - Lee Revell, 2005.03.30
25 fairly self explanatory - select Duplex, then for capture and playback select
26 the multichannel devices, set the in and out channels to 16, and the sample
30 /usr/local/bin/jackd -R -dalsa -r48000 -p64 -n2 -D -Chw:0,2 -Phw:0,3 -S
32 This will give you 16 input ports and 16 output ports.
34 The 16 output ports map onto the 16 FX buses (or the first 16 of 64, for the
36 sb-live-mixer.rst (or audigy-mixer.rst).
38 The 16 input ports are connected to the 16 physical inputs. Contrary to
48 the second and third input ports are wired to the center/LFE output. You will
52 ports to FXBUS2 (multitrack recording input) and EXTOUT (physical output)
/Documentation/networking/
Dplip.rst1 .. SPDX-License-Identifier: GPL-2.0
14 -----------------
17 This device interface allows a point-to-point connection between two
18 parallel ports to appear as a IP network interface.
25 printer port. PLIP is a non-standard, but [can use] uses the standard
26 LapLink null-printer cable [can also work in turbo mode, with a PLIP
62 -------------------
66 share parallel ports between PLIP and other services.
77 On these machines, the PLIP driver can be used in IRQ-less mode, where
82 indicate that there isn't a noticeable performance drop when using IRQ-less
[all …]
Dswitchdev.rst1 .. SPDX-License-Identifier: GPL-2.0
10 Copyright |copy| 2014-2015 Scott Feldman <sfeldma@gmail.com>
13 The Ethernet switch device driver model (switchdev) is an in-kernel driver
18 an example setup using a data-center-class switch ASIC chip. Other setups
19 with SR-IOV or soft switches, such as OVS, are possible.
24 User-space tools
27 +-------------------------------------------------------------------+
30 +--------------+-------------------------------+
34 +----------------------------------------------+
40 +--+----+----+----+----+----+---+ +-----+-----+
[all …]
/Documentation/devicetree/bindings/ata/
Dcortina,gemini-sata-bridge.txt3 The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
5 them in different configurations to two SATA ports.
8 - compatible: should be
9 "cortina,gemini-sata-bridge"
10 - reg: registers and size for the block
11 - resets: phandles to the reset lines for both SATA bridges
12 - reset-names: must be "sata0", "sata1"
13 - clocks: phandles to the compulsory peripheral clocks
14 - clock-names: must be "SATA0_PCLK", "SATA1_PCLK"
15 - syscon: a phandle to the global Gemini system controller
[all …]
/Documentation/devicetree/bindings/display/bridge/
Drenesas,dw-hdmi.txt9 following device-specific properties.
14 - compatible : Shall contain one or more of
15 - "renesas,r8a774a1-hdmi" for R8A774A1 (RZ/G2M) compatible HDMI TX
16 - "renesas,r8a774b1-hdmi" for R8A774B1 (RZ/G2N) compatible HDMI TX
17 - "renesas,r8a774e1-hdmi" for R8A774E1 (RZ/G2H) compatible HDMI TX
18 - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
19 - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
20 - "renesas,r8a77961-hdmi" for R8A77961 (R-Car M3-W+) compatible HDMI TX
21 - "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX
22 - "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 and RZ/G2 compatible
[all …]
/Documentation/devicetree/bindings/display/ti/
Dti,opa362.txt4 - compatible: "ti,opa362"
5 - enable-gpios: enable/disable output gpio
8 - Video port 0 for opa362 input
9 - Video port 1 for opa362 output
15 enable-gpios = <&gpio1 23 0>; /* GPIO to enable video out amplifier */
17 ports {
18 #address-cells = <1>;
19 #size-cells = <0>;
24 remote-endpoint = <&venc_out>;
31 remote-endpoint = <&tv_connector_in>;
/Documentation/ABI/testing/
Ddebugfs-cros-ec1 What: /sys/kernel/debug/<cros-ec-device>/console_log
8 write it out to some logs.
10 What: /sys/kernel/debug/<cros-ec-device>/panicinfo
18 What: /sys/kernel/debug/<cros-ec-device>/pdinfo
23 information for all the USB PD/type-C ports available. If
24 the are no ports available, this file will be just an empty
27 What: /sys/kernel/debug/<cros-ec-device>/uptime
36 What: /sys/kernel/debug/<cros-ec-device>/last_resume_result
/Documentation/devicetree/bindings/gpio/
Dnvidia,tegra186-gpio.txt36 The number of ports implemented by each GPIO controller varies. The number of
38 are grouped and laid out according to the port they affect.
42 extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
43 describes the port-level mapping. In that file, the naming convention for ports
49 represents the aggregate status for all GPIOs within a set of ports. Thus, the
51 of the number of ports it implements. Note that the HW documentation refers to
52 both the overall controller HW module and the sets-of-ports as "controllers".
55 of ports. Each GPIO may be configured to feed into a specific one of the
56 interrupt signals generated by a set-of-ports. The intent is for each generated
59 per-port-set signals is reported via a separate register. Thus, a driver needs
[all …]
/Documentation/networking/dsa/
Dsja1105.rst10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
17 These are SPI-managed automotive switches, with all ports being gigabit
21 set-and-forget use, with minimal dynamic interaction at runtime. They
56 Also the configuration is write-only (software cannot read it back from the
71 programmable filters for link-local destination MACs.
[all …]
Ddsa.rst22 An Ethernet switch is typically comprised of multiple front-panel ports, and one
27 gateways, or even top-of-the rack switches. This host Ethernet controller will
33 ports are referred to as "dsa" ports in DSA terminology and code. A collection
36 For each front-panel port, DSA will create specialized network devices which are
37 used as controlling and data-flowing endpoints for use by the Linux networking
43 Ethernet frames it received to/from specific ports to help the management
44 interface figure out:
46 - what port is this frame coming from
47 - what was the reason why this frame got forwarded
48 - how to send CPU originated traffic to specific ports
[all …]
/Documentation/hwmon/
Dit87.rst10 Addresses scanned: from Super I/O config space (8 I/O ports)
18 Addresses scanned: from Super I/O config space (8 I/O ports)
24 Addresses scanned: from Super I/O config space (8 I/O ports)
32 Addresses scanned: from Super I/O config space (8 I/O ports)
40 Addresses scanned: from Super I/O config space (8 I/O ports)
48 Addresses scanned: from Super I/O config space (8 I/O ports)
56 Addresses scanned: from Super I/O config space (8 I/O ports)
64 Addresses scanned: from Super I/O config space (8 I/O ports)
72 Addresses scanned: from Super I/O config space (8 I/O ports)
80 Addresses scanned: from Super I/O config space (8 I/O ports)
[all …]
/Documentation/m68k/
Dbuddha-driver.rst8 ------------------------------------------------------------------------
11 Buddha-part of the Catweasel Zorro-II version
15 example leaving some address lines out of the equations...).
21 product number: 0 (42 for Catweasel Z-II)
23 Rom-vector: $1000
25 The card should be a Z-II board, size 64K, not for freemem
26 list, Rom-Vektor is valid, no second Autoconfig-board on the
30 as the Amiga Kickstart does: The lower nibble of the 8-Bit
36 otherwise your chance is only 1:16 to find the board :-).
38 The local memory-map is even active when mapped to $e8:
[all …]
/Documentation/driver-api/usb/
Dpower-management.rst1 .. _usb-power-management:
7 :Date: Last-updated: February 2014
11 ---------
17 * Changing the default idle-delay time
31 -------------------------
35 component is ``suspended`` it is in a nonfunctional low-power state; it
37 ``resumed`` (returned to a functional full-power state) when the kernel
67 ----------------------
85 --------------------------
101 -------------------
[all …]
/Documentation/devicetree/bindings/net/dsa/
Drealtek-smi.txt1 Realtek SMI-based Switches
4 The SMI "Simple Management Interface" is a two-wire protocol using
5 bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does
7 SMI-based Realtek devices.
11 - compatible: must be exactly one of:
13 "realtek,rtl8366rb" (4+1 ports)
14 "realtek,rtl8366s" (4+1 ports)
22 - mdc-gpios: GPIO line for the MDC clock line.
23 - mdio-gpios: GPIO line for the MDIO data line.
24 - reset-gpios: GPIO line for the reset signal.
[all …]
Dmt7530.txt6 - compatible: may be compatible = "mediatek,mt7530"
9 - #address-cells: Must be 1.
10 - #size-cells: Must be 0.
11 - mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
12 on multi-chip module belong to MT7623A has or the remotely standalone
17 - core-supply: Phandle to the regulator node necessary for the core power.
18 - io-supply: Phandle to the regulator node necessary for the I/O power.
19 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
24 - reset-gpios: Should be a gpio specifier for a reset line.
28 - resets : Phandle pointing to the system reset controller with
[all …]
/Documentation/devicetree/bindings/media/
Dsamsung-fimc.txt2 ----------------------------------------------
4 The S5P/Exynos SoC Camera subsystem comprises of multiple sub-devices
6 the S5P SoCs series known as CAMIF), MIPI CSIS, FIMC-LITE and FIMC-IS (ISP).
8 The sub-subdevices are defined as child nodes of the common 'camera' node which
10 any single sub-device, like common camera port pins or the CAMCLK clock outputs
14 --------------------
18 - compatible: must be "samsung,fimc", "simple-bus"
19 - clocks: list of clock specifiers, corresponding to entries in
20 the clock-names property;
21 - clock-names : must contain "sclk_cam0", "sclk_cam1", "pxl_async0",
[all …]
/Documentation/devicetree/bindings/media/xilinx/
Dxlnx,csi2rxss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx MIPI CSI-2 Receiver Subsystem
10 - Vishal Sagar <vishal.sagar@xilinx.com>
13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
16 The subsystem consists of a MIPI D-PHY in slave mode which captures the
17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
21 Please note that this bindings includes only the MIPI CSI-2 Rx controller
[all …]
/Documentation/driver-api/gpio/
Dbt8xxgpio.rst2 A driver for a selfmade cheap BT8xx based PCI GPIO-card (bt8xxgpio)
7 A generic digital 24-port PCI GPIO card can be built out of an ordinary
12 The bt8xx chip does have 24 digital GPIO ports.
13 These ports are accessible via 24 pins on the SMD chip package.
25 The GPIO pins are marked with G00-G23::
31 ---------------------------------------------------------------------------
32 --| ^ ^ |--
33 --| pin 86 pin 67 |--
34 --| |--
35 --| pin 61 > |-- G18
[all …]
/Documentation/networking/device_drivers/cable/
Dsb1000.rst1 .. SPDX-License-Identifier: GPL-2.0
10 It's a one-way downstream-only cable modem, meaning that your upstream net link
36 - http://web.archive.org/web/%2E/http://home.adelphia.net/~siglercm/sb1000.html
37 - http://web.archive.org/web/%2E/http://linuxpower.cx/~cable/
75 of "pnpdump" to a file and editing this file to set the correct I/O ports,
79 errors and fix as necessary. (As an aside, I use I/O ports 0x110 and
84 6. Download the original file sb1000-1.1.2.tar.gz from Franco's site or one of
86 and do a ``make cmconfig`` and then ``install -c cmconfig /usr/local/sbin``.
92 already in there. Then modify ppp@gi-on to set the correct login name,
93 phone number, and frequency for the cable modem. Also edit pap-secrets
[all …]
/Documentation/trace/
Dintel_th.rst1 .. SPDX-License-Identifier: GPL-2.0
8 --------
12 sources over several types of trace output ports encoded in System
23 - Software Trace Hub (STH), trace source, which is a System Trace
25 - Memory Storage Unit (MSU), trace output, which allows storing
27 - Parallel Trace Interface output (PTI), trace output to an external
29 - Global Trace Hub (GTH), which is a switch and a central component
33 Documentation/ABI/testing/sysfs-bus-intel_th-output-devices, the most
37 GTH allows directing different STP masters into different output ports
39 description is at Documentation/ABI/testing/sysfs-bus-intel_th-devices-gth.
[all …]
/Documentation/PCI/
Dpcieaer-howto.rst1 .. SPDX-License-Identifier: GPL-2.0
8 :Authors: - T. Long Nguyen <tom.l.nguyen@intel.com>
9 - Yanmin Zhang <yanmin.zhang@intel.com>
17 ----------------
26 -----------------------------------
41 - Gathers the comprehensive error information if errors occurred.
42 - Reports error to the users.
43 - Performs error recovery actions.
45 AER driver only attaches root ports which support PCI-Express AER
53 -------------------------------------------------------------
[all …]

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