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/Documentation/PCI/endpoint/
Dpci-endpoint.rst5 This document is a guide to use the PCI Endpoint Framework in order to create
12 Linux has a comprehensive PCI subsystem to support PCI controllers that
13 operates in Root Complex mode. The subsystem has capability to scan PCI bus,
14 assign memory resources and IRQ resources, load PCI driver (based on
18 However the PCI controller IP integrated in some SoCs is capable of operating
19 either in Root Complex mode or Endpoint mode. PCI Endpoint Framework will
24 PCI Endpoint Core
27 The PCI Endpoint Core layer comprises 3 components: the Endpoint Controller
31 PCI Endpoint Controller(EPC) Library
38 APIs for the PCI controller Driver
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Dindex.rst4 PCI Endpoint Framework
10 pci-endpoint
11 pci-endpoint-cfs
12 pci-test-function
13 pci-test-howto
15 function/binding/pci-test
Dpci-test-howto.rst4 PCI Test User Guide
9 This document is a guide to help users use pci-epf-test function driver
10 and pci_endpoint_test host driver for testing PCI. The list of steps to
35 # ls /sys/bus/pci-epf/drivers
44 Creating pci-epf-test Device
47 PCI endpoint function device can be created using the configfs. To create
48 pci-epf-test device, the following commands can be used::
54 The "mkdir func1" above creates the pci-epf-test function device that will
57 The PCI endpoint framework populates the directory with the following
65 The PCI endpoint function driver populates these entries with default values
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/Documentation/driver-api/pci/
Dpci.rst1 PCI Support Library
4 .. kernel-doc:: drivers/pci/pci.c
7 .. kernel-doc:: drivers/pci/pci-driver.c
10 .. kernel-doc:: drivers/pci/remove.c
13 .. kernel-doc:: drivers/pci/search.c
16 .. kernel-doc:: drivers/pci/msi.c
19 .. kernel-doc:: drivers/pci/bus.c
22 .. kernel-doc:: drivers/pci/access.c
25 .. kernel-doc:: drivers/pci/irq.c
28 .. kernel-doc:: drivers/pci/probe.c
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/Documentation/PCI/
Dpciebus-howto.rst5 The PCI Express Port Bus Driver Guide HOWTO
14 This guide describes the basics of the PCI Express Port Bus driver
16 register/unregister with the PCI Express Port Bus Driver.
19 What is the PCI Express Port Bus Driver
22 A PCI Express Port is a logical PCI-PCI Bridge structure. There
23 are two types of PCI Express Port: the Root Port and the Switch
24 Port. The Root Port originates a PCI Express link from a PCI Express
25 Root Complex and the Switch Port connects PCI Express links to
26 internal logical PCI buses. The Switch Port, which has its secondary
30 PCI Express link from the PCI Express Switch.
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Dpcieaer-howto.rst5 The PCI Express Advanced Error Reporting Driver Guide HOWTO
19 This guide describes the basics of the PCI Express Advanced Error
22 PCI Express AER driver.
25 What is the PCI Express AER Driver?
28 PCI Express error signaling can occur on the PCI Express link itself
29 or on behalf of transactions initiated on the link. PCI Express
32 required of all PCI Express components providing a minimum defined
34 capability is implemented with a PCI Express advanced error reporting
37 The PCI Express AER driver provides the infrastructure to support PCI
38 Express Advanced Error Reporting capability. The PCI Express AER
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Dpci.rst4 How To Write Linux PCI Drivers
10 The world of PCI is vast and full of (mostly unpleasant) surprises.
11 Since each CPU architecture implements different chip-sets and PCI devices
12 have different requirements (erm, "features"), the result is the PCI support
15 PCI device drivers.
25 Please send questions/comments/patches about Linux PCI API to the
26 "Linux PCI" <linux-pci@atrey.karlin.mff.cuni.cz> mailing list.
29 Structure of PCI drivers
31 PCI drivers "discover" PCI devices in a system via pci_register_driver().
32 Actually, it's the other way around. When the PCI generic code discovers
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Dsysfs-pci.rst4 Accessing PCI device resources through sysfs
7 sysfs, usually mounted at /sys, provides access to PCI resources on platforms
30 The topmost element describes the PCI domain and bus number. In this case,
39 class PCI class (ascii, ro)
40 config PCI config space (binary, rw)
41 device PCI device (ascii, ro)
46 resource PCI resource host addresses (ascii, ro)
47 resource0..N PCI resource N, if present (binary, mmap, rw\ [1]_)
48 resource0_wc..N_wc PCI WC map resource N, if prefetchable (binary, mmap)
49 revision PCI revision (ascii, ro)
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/Documentation/ABI/testing/
Dsysfs-bus-pci1 What: /sys/bus/pci/drivers/.../bind
3 Contact: linux-pci@vger.kernel.org
10 found in /sys/bus/pci/devices/. For example::
12 # echo 0000:00:19.0 > /sys/bus/pci/drivers/foo/bind
16 What: /sys/bus/pci/drivers/.../unbind
18 Contact: linux-pci@vger.kernel.org
25 found in /sys/bus/pci/devices/. For example::
27 # echo 0000:00:19.0 > /sys/bus/pci/drivers/foo/unbind
31 What: /sys/bus/pci/drivers/.../new_id
33 Contact: linux-pci@vger.kernel.org
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Dsysfs-bus-pci-devices-aer_stats12 What: /sys/bus/pci/devices/<dev>/aer_dev_correctable
15 Contact: linux-pci@vger.kernel.org, rajatja@google.com
17 PCI device using ERR_COR. Note that since multiple errors may
33 What: /sys/bus/pci/devices/<dev>/aer_dev_fatal
36 Contact: linux-pci@vger.kernel.org, rajatja@google.com
38 PCI device using ERR_FATAL. Note that since multiple errors may
63 What: /sys/bus/pci/devices/<dev>/aer_dev_nonfatal
66 Contact: linux-pci@vger.kernel.org, rajatja@google.com
68 PCI device using ERR_NONFATAL. Note that since multiple errors
99 (internally) the ERR_* messages for errors seen by the internal rootport PCI
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/Documentation/devicetree/bindings/pinctrl/
Dmarvell,orion-pinctrl.txt24 mpp0 0 pcie(rstout), pci(req2), gpio
25 mpp1 1 gpio, pci(gnt2)
26 mpp2 2 gpio, pci(req3), pci-1(pme)
27 mpp3 3 gpio, pci(gnt3)
28 mpp4 4 gpio, pci(req4)
29 mpp5 5 gpio, pci(gnt4)
30 mpp6 6 gpio, pci(req5), pci-1(clk)
31 mpp7 7 gpio, pci(gnt5), pci-1(clk)
49 mpp0 0 pcie(rstout), pci(req2), gpio
50 mpp1 1 gpio, pci(gnt2)
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/Documentation/devicetree/bindings/pci/
Dralink,rt3883-pci.txt1 * Mediatek/Ralink RT3883 PCI controller
7 - compatible: must be "ralink,rt3883-pci"
29 interrupt controller and the PCI host bridge.
48 b) PCI host bridge:
61 - device_type: must be "pci"
63 - bus-range: PCI bus numbers covered
65 - ranges: specifies the ranges for the PCI memory and I/O regions
68 - interrupt-map: standard PCI properties to define the mapping of the
69 PCI interface to interrupt numbers.
71 The PCI host bridge node might have additional sub-nodes representing
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Dfsl,pci.txt1 * Bus Enumeration by Freescale PCI-X Agent
3 Typically any Freescale PCI-X bridge hardware strapped into Agent mode
5 all mezzanines to be PCI-X Agents, but one per system may still
8 The property defined below will allow a PCI-X bridge to be used for bus
12 - fsl,pci-agent-force-enum : There is no value associated with this
17 /* PCI-X bridge known to be PrPMC Monarch */
18 pci0: pci@ef008000 {
19 fsl,pci-agent-force-enum;
23 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
24 device_type = "pci";
Dpci-rcar-gen2.txt1 Renesas AHB to PCI bridge
9 - compatible: "renesas,pci-r8a7742" for the R8A7742 SoC;
10 "renesas,pci-r8a7743" for the R8A7743 SoC;
11 "renesas,pci-r8a7744" for the R8A7744 SoC;
12 "renesas,pci-r8a7745" for the R8A7745 SoC;
13 "renesas,pci-r8a7790" for the R8A7790 SoC;
14 "renesas,pci-r8a7791" for the R8A7791 SoC;
15 "renesas,pci-r8a7793" for the R8A7793 SoC;
16 "renesas,pci-r8a7794" for the R8A7794 SoC;
17 "renesas,pci-rcar-gen2" for a generic R-Car Gen2 or
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Dloongson.yaml4 $id: http://devicetree.org/schemas/pci/loongson.yaml#
7 title: Loongson PCI Host Controller
13 PCI host controller found on Loongson PCHs and SoCs.
16 - $ref: /schemas/pci/pci-bus.yaml#
21 - const: loongson,ls2k-pci
22 - const: loongson,ls7a-pci
23 - const: loongson,rs780e-pci
51 compatible = "loongson,rs780e-pci";
52 device_type = "pci";
Dhost-generic-pci.yaml4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
7 title: Generic PCI host controller
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
23 geography of a PCI bus address by concatenating the various components to
46 - const: pci-host-ecam-generic
48 ThunderX PCI host controller for pass-1.x silicon
50 Firmware-initialized PCI host controller to on-chip devices found on
55 const: cavium,pci-host-thunder-ecam
58 const: cavium,pci-host-thunder-pem
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D83xx-512x-pci.txt1 * Freescale 83xx and 512x PCI bridges
3 Freescale 83xx and 512x SOCs include the same PCI bridge core.
7 The first is for the internal PCI bridge registers
8 The second is for the PCI config space access registers
11 pci0: pci@e0008500 {
14 /* IDSEL 0x0E -mini PCI */
20 /* IDSEL 0x0F - PCI slot */
37 compatible = "fsl,mpc8349-pci";
38 device_type = "pci";
Dpci-iommu.txt2 relationship between PCI(e) devices and IOMMU(s).
4 Each PCI(e) device under a root complex is uniquely identified by its Requester
16 IOMMUs may distinguish PCI devices through sideband data derived from the
17 Requester ID. While a given PCI device can only master through one IOMMU, a
22 and a mechanism is required to map from a PCI device to its IOMMU and sideband
29 PCI root complex
61 pci: pci@f {
64 device_type = "pci";
88 pci: pci@f {
91 device_type = "pci";
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Dpci-keystone.txt3 Keystone PCI host Controller is based on the Synopsys DesignWare PCI
6 Documentation/devicetree/bindings/pci/designware-pcie.txt
8 Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
23 interrupts: GIC interrupt lines connected to PCI MSI interrupt lines
25 msi-map: As specified in Documentation/devicetree/bindings/pci/pci-msi.txt
31 PCI in either RC mode or EP mode.
63 phys: phandle to generic Keystone SerDes PHY for PCI
64 phy-names: name of the generic Keystone SerDes PHY for PCI
65 - If boot loader already does PCI link establishment, then phys and
69 DesignWare DT Properties not applicable for Keystone PCI
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/Documentation/scsi/
Daic7xxx.rst27 aic7850 10 PCI/32 10MHz 8Bit 3
28 aic7855 10 PCI/32 10MHz 8Bit 3
29 aic7856 10 PCI/32 10MHz 8Bit 3
30 aic7859 10 PCI/32 20MHz 8Bit 3
31 aic7860 10 PCI/32 20MHz 8Bit 3
32 aic7870 10 PCI/32 10MHz 16Bit 16
33 aic7880 10 PCI/32 20MHz 16Bit 16
34 aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8
35 aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8
36 aic7892 20 PCI/64-66 80MHz 16Bit 16 3 4 5 6 7 8
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Dadvansys.rst9 (8-bit transfer) SCSI Host Adapters for the ISA, EISA, VL, and PCI
11 transfer) SCSI Host Adapters for the PCI bus.
27 - ABP902/3902 - Bus-Master PCI (16 CDB)
28 - ABP3905 - Bus-Master PCI (16 CDB)
29 - ABP915 - Bus-Master PCI (16 CDB)
30 - ABP920 - Bus-Master PCI (16 CDB)
31 - ABP3922 - Bus-Master PCI (16 CDB)
32 - ABP3925 - Bus-Master PCI (16 CDB)
33 - ABP930 - Bus-Master PCI (16 CDB)
34 - ABP930U - Bus-Master PCI Ultra (16 CDB)
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/Documentation/devicetree/bindings/virtio/
Diommu.txt1 * virtio IOMMU PCI device
3 When virtio-iommu uses the PCI transport, its programming interface is
4 discovered dynamically by the PCI probing infrastructure. However the
6 masters. Therefore, the PCI root complex that hosts the virtio-iommu
11 - compatible: Should be "virtio,pci-iommu"
12 - reg: PCI address of the IOMMU. As defined in the PCI Bus
31 compatible = "pci-host-ecam-generic";
36 compatible = "virtio,pci-iommu";
42 * The IOMMU manages all functions in this PCI domain except
50 compatible = "pci-host-ecam-generic";
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/Documentation/powerpc/
Deeh-pci-error-recovery.rst2 PCI Bus EEH Error Recovery
12 The IBM POWER-based pSeries and iSeries computers include PCI bus
14 reporting a large variety of PCI bus error conditions. These features
16 hardware features allow PCI bus errors to be cleared and a PCI
20 This is in contrast to traditional PCI error handling, where the
21 PCI chip is wired directly to the CPU, and an error would cause
27 reliable and robust by protecting it from PCI errors, and giving
28 the OS the ability to "reboot"/recover individual PCI devices.
30 Future systems from other vendors, based on the PCI-E specification,
37 as PCI cards dying from heat, humidity, dust, vibration and bad
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/Documentation/s390/
Dpci.rst4 S/390 PCI
21 Do not use PCI Mapped I/O (MIO) instructions.
25 Ignore the RID field and force use of one PCI domain per PCI function.
37 Holds messages from the processing of PCI events, like machine check handling
50 * /sys/bus/pci/slots/XXXXXXXX
53 PCI function.
55 - /sys/bus/pci/slots/XXXXXXXX/power
59 echo 0 > /sys/bus/pci/devices/XXXX:XX:XX.X/sriov_numvf
61 * /sys/bus/pci/devices/XXXX:XX:XX.X/
67 Low-level identifier used for a configured PCI function.
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/Documentation/power/
Dpci.rst2 PCI Power Management
7 An overview of concepts and the Linux kernel's interfaces related to PCI power
11 This document only covers the aspects of power management specific to PCI
18 1. Hardware and Platform Support for PCI Power Management
19 2. PCI Subsystem and Device Power Management
20 3. PCI Device Drivers and Power Management
24 1. Hardware and Platform Support for PCI Power Management
41 PCI devices may be put into low-power states in two ways, by using the device
42 capabilities introduced by the PCI Bus Power Management Interface Specification,
44 approach, that is referred to as the native PCI power management (native PCI PM)
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