Searched full:phase (Results 1 – 25 of 143) sorted by relevance
123456
| /Documentation/hwmon/ |
| D | max16601.rst | 64 curr2_input VCORE phase 0 input current.
67 curr3_input VCORE phase 1 input current.
70 curr4_input VCORE phase 2 input current.
73 curr5_input VCORE phase 3 input current.
76 curr6_input VCORE phase 4 input current.
79 curr7_input VCORE phase 5 input current.
82 curr8_input VCORE phase 6 input current.
85 curr9_input VCORE phase 7 input current.
101 curr13_input VCORE phase 0 output current.
104 curr14_input VCORE phase 1 output current.
[all …]
|
| D | pmbus-core.rst | 165 int (*read_word_data)(struct i2c_client *client, int page, int phase,
168 Read word from page <page>, phase <pase>, register <reg>. If the chip does not
169 support multiple phases, the phase parameter can be ignored. If the chip
170 supports multiple phases, a phase value of 0xff indicates all phases.
207 int pmbus_set_page(struct i2c_client *client, u8 page, u8 phase);
209 Set PMBus page register to <page> and <phase> for subsequent commands.
210 If the chip does not support multiple phases, the phase parameter is
211 ignored. Otherwise, a phase value of 0xff selects all phases.
215 int pmbus_read_word_data(struct i2c_client *client, u8 page, u8 phase,
218 Read word data from <page>, <phase>, <reg>. Similar to
[all …]
|
| D | mp2975.rst | 20 vendor dual-loop, digital, multi-phase controller MP2975.
26 to 8-phase operation for rail 1 and up to 4-phase operation for rail
54 - for phase current: input and label.
|
| D | tps53679.rst | 55 Chips in this series are multi-phase step-down converters with one or two
158 digit is the phase within the channel. Per-phase
176 non-phase telemetry (iout1, iout2).
|
| /Documentation/devicetree/bindings/mmc/ |
| D | exynos-dw-mshc.txt | 30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
31 in transmit mode and CIU clock phase shift value in receive mode for single
35 * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
36 in transmit mode and CIU clock phase shift value in receive mode for double
39 * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
45 - First Cell: CIU clock phase shift value for tx mode.
46 - Second Cell: CIU clock phase shift value for rx mode.
49 - valid value for tx phase shift and rx phase shift is 0 to 7.
50 - when CIU clock divider value is set to 3, all possible 8 phase shift
53 phase shift clocks should be 0.
|
| D | hi3798cv200-dw-mshc.txt | 19 "ciu-sample" - Hi3798CV200 extended phase clock for ciu sampling.
20 "ciu-drive" - Hi3798CV200 extended phase clock for ciu driving.
|
| /Documentation/networking/device_drivers/appletalk/ |
| D | cops.rst | 66 dummy -seed -phase 2 -net 2000 -addr 2000.10 -zone "1033"
67 lt0 -seed -phase 1 -net 1000 -addr 1000.50 -zone "1033"
71 eth0 -seed -phase 2 -net 3000 -addr 3000.20 -zone "1033"
72 lt0 -seed -phase 1 -net 1000 -addr 1000.50 -zone "1033"
78 lt0 -seed -phase 1 -net 1000 -addr 1000.10 -zone "LocalTalk1"
79 lt1 -seed -phase 1 -net 2000 -addr 2000.20 -zone "LocalTalk2"
80 eth0 -seed -phase 2 -net 3000 -addr 3000.30 -zone "EtherTalk"
|
| /Documentation/devicetree/bindings/sound/ |
| D | max98504.txt | 20 applied during the "attack hold" and "timed hold" phase, the value must be
22 - maxim,brownout-attack-hold-ms - the brownout attack hold phase time in ms,
24 - maxim,brownout-timed-hold-ms - the brownout timed hold phase time in ms,
26 - maxim,brownout-release-rate-ms - the brownout release phase step time in ms,
|
| /Documentation/devicetree/bindings/leds/backlight/ |
| D | sky81452-backlight.txt | 14 - skyworks,phase-shift : Enable phase shift mode
27 skyworks,phase-shift;
|
| /Documentation/devicetree/bindings/mfd/ |
| D | axp20x.txt | 126 DCDC2 : DC-DC buck : vin2-supply : poly-phase capable
127 DCDC3 : DC-DC buck : vin3-supply : poly-phase capable
129 DCDC5 : DC-DC buck : vin5-supply : poly-phase capable
130 DCDC6 : DC-DC buck : vin6-supply : poly-phase capable
153 DCDCA : DC-DC buck : vina-supply : poly-phase capable
154 DCDCB : DC-DC buck : vinb-supply : poly-phase capable
155 DCDCC : DC-DC buck : vinc-supply : poly-phase capable
156 DCDCD : DC-DC buck : vind-supply : poly-phase capable
157 DCDCE : DC-DC buck : vine-supply : poly-phase capable
170 Additionally, the AXP806 DC-DC regulators support poly-phase arrangements
[all …]
|
| /Documentation/devicetree/bindings/clock/ |
| D | altr_socfpga.txt | 26 - clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
28 value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
|
| /Documentation/driver-api/pm/ |
| D | devices.rst | 234 always go together, and both are multi-phase operations.
271 sleep states and the hibernation state ("suspend-to-disk"). Each phase involves
272 executing callbacks for every device before the next phase begins. Not all
285 rules are used to determine which callback to execute in the given phase:
318 1. The ``prepare`` phase is meant to prevent races by preventing new
323 suspend-related phases, during the ``prepare`` phase the device
393 4. The ``suspend_noirq`` phase occurs after IRQ handlers have been disabled,
402 an error during the suspend phase by fielding a shared interrupt
432 generally means undoing the actions of the ``suspend_noirq`` phase. If
446 the preceding ``suspend_late`` phase.
[all …]
|
| /Documentation/devicetree/bindings/spi/ |
| D | spi-samsung.txt | 61 - samsung,spi-feedback-delay: The sampling phase shift to be applied on the
65 - 0: No phase shift.
66 - 1: 90 degree phase shift sampling.
67 - 2: 180 degree phase shift sampling.
68 - 3: 270 degree phase shift sampling.
|
| /Documentation/devicetree/bindings/iio/frequency/ |
| D | adf4350.txt | 22 - adi,phase-detector-polarity-positive-enable: Enables positive phase
54 2: Phase resync enable
82 adi,phase-detector-polarity-positive-enable;
|
| /Documentation/devicetree/bindings/iio/dac/ |
| D | ad5755.txt | 23 - adi,dc-dc-phase:
24 Valid values for DC DC Phase control is:
31 clock 90 degrees out of phase from each other.
97 adi,dc-dc-phase = <0>;
|
| /Documentation/devicetree/bindings/power/supply/ |
| D | rohm,bd99954.yaml | 35 # First a constant current (5) phase (CC)
36 # Then constant voltage (CV) phase (after the battery voltage has reached
70 # Current used at trickle-charge phase (8 in above chart)
75 # Current used at pre-charge phase (6 in above chart)
80 # Current used at fast charge constant current phase (5 in above chart)
85 # The constant voltage used in fast charging phase (4 in above chart)
|
| /Documentation/admin-guide/mm/ |
| D | memory-hotplug.rst | 47 1) Physical Memory Hotplug phase
48 2) Logical Memory Hotplug phase.
50 The First phase is to communicate hardware/firmware and make/erase
51 environment for hotplugged memory. Basically, this phase is necessary
52 for the purpose (B), but this is good phase for communication between
59 this phase is triggered automatically. ACPI can notify this event. If not,
63 Logical Memory Hotplug phase is to change memory state into
65 changed by this phase. The kernel makes all memory in it as free pages
68 In this document, this phase is described as online/offline.
70 Logical Memory Hotplug phase is triggered by write of sysfs file by system
[all …]
|
| /Documentation/devicetree/bindings/memory-controllers/ |
| D | st,stm32-fmc2-ebi.yaml | 132 phase in nanoseconds used for asynchronous read/write transactions.
136 phase in nanoseconds used for asynchronous multiplexed read/write
140 description: This property defines the duration of the data setup phase
148 description: This property defines the duration of the data hold phase
161 phase in nanoseconds used for asynchronous write transactions.
165 phase in nanoseconds used for asynchronous multiplexed write
170 phase in nanoseconds used for asynchronous write transactions.
177 description: This property defines the duration of the data hold phase
|
| /Documentation/driver-api/media/drivers/ |
| D | radiotrack.rst | 105 0 0 "zero" bit phase 1
106 0 1 "zero" bit phase 2
107 1 0 "one" bit phase 1
108 1 1 "one" bit phase 2
161 disable, "zero" bit phase 1, tuner adjust)
163 disable, "zero" bit phase 2, tuner adjust)
166 disable, "one" bit phase 1, tuner adjust)
168 disable, "one" bit phase 2, tuner adjust)
|
| /Documentation/devicetree/bindings/regulator/ |
| D | mps,mpq7920.yaml | 60 mps,buck-phase-delay:
64 defines the phase delay of this buck, must be one of the following
104 mps,buck-phase-delay = /bits/ 8 <2>;
|
| /Documentation/admin-guide/pm/ |
| D | suspend-flows.rst | 81 information on what exactly happens in each phase).
83 Every device is visited in each phase, but typically it is not physically
87 phase and high-level ("action") interrupt handlers are prevented from being
88 invoked before the *noirq* suspend phase.
141 information on what exactly happens in each phase).
143 Every device is visited in each phase, but typically it is not physically
147 phase and the runtime PM API is re-enabled for every device whose driver
148 supports it during the *early* resume phase.
|
| /Documentation/devicetree/bindings/mtd/ |
| D | amlogic,meson-nand.txt | 17 "rx" - rx clock phase
18 "tx" - tx clock phase
|
| /Documentation/power/ |
| D | suspend-and-interrupts.rst | 13 suspend after the "late" phase of suspending devices (that is, after all of the
17 The rationale for doing so is that after the "late" phase of device suspend
26 of suspend_device_irqs(), along with the "noirq" phase of device suspend and
29 Device IRQs are re-enabled during system resume, right before the "early" phase
101 interrupts right after the "noirq" phase of suspending devices.
|
| /Documentation/cpu-freq/ |
| D | core.rst | 54 The phase is specified in the second argument to the notifier. The phase is
70 The second argument specifies the phase - CPUFREQ_PRECHANGE or
|
| /Documentation/devicetree/bindings/display/ |
| D | ssd1307fb.txt | 27 - solomon,prechargep1: Length of deselect period (phase 1) in clock cycles.
28 - solomon,prechargep2: Length of precharge period (phase 2) in clock cycles.
|
123456