| /Documentation/driver-api/phy/ |
| D | phy.rst | 2 PHY subsystem
7 This document explains the Generic PHY Framework along with the APIs provided,
13 *PHY* is the abbreviation for physical layer. It is used to connect a device
14 to the physical medium e.g., the USB controller has a PHY to provide functions
17 controllers have PHY functionality embedded into it and others use an external
18 PHY. Other peripherals that use PHY include Wireless LAN, Ethernet,
21 The intention of creating this framework is to bring the PHY drivers spread
22 all over the Linux kernel to drivers/phy to increase code re-use and for
25 This framework will be of use only to devices that use external PHY (PHY
28 Registering/Unregistering the PHY provider
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| /Documentation/devicetree/bindings/phy/ |
| D | qcom,qmp-phy.yaml | 5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
8 title: Qualcomm QMP PHY controller
14 QMP phy controller supports physical layer functionality for a number of
20 - qcom,ipq8074-qmp-pcie-phy
21 - qcom,ipq8074-qmp-usb3-phy
22 - qcom,msm8996-qmp-pcie-phy
23 - qcom,msm8996-qmp-ufs-phy
24 - qcom,msm8996-qmp-usb3-phy
25 - qcom,msm8998-qmp-pcie-phy
26 - qcom,msm8998-qmp-ufs-phy
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| D | samsung-phy.txt | 6 - "samsung,s5pv210-mipi-video-phy"
7 - "samsung,exynos5420-mipi-video-phy"
8 - "samsung,exynos5433-mipi-video-phy"
9 - #phy-cells : from the generic phy bindings, must be 1;
14 In case of exynos5433 compatible PHY:
20 For "samsung,s5pv210-mipi-video-phy" compatible PHYs the second cell in
21 the PHY specifier identifies the PHY and its meaning is as follows:
26 "samsung,exynos5420-mipi-video-phy" and "samsung,exynos5433-mipi-video-phy"
27 supports additional fifth PHY:
30 Samsung Exynos SoC series Display Port PHY
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| D | brcm,stingray-usb-phy.txt | 1 Broadcom Stingray USB PHY
5 - "brcm,sr-usb-combo-phy" is combo PHY has two PHYs, one SS and one HS.
6 - "brcm,sr-usb-hs-phy" is a single HS PHY.
7 - reg: offset and length of the PHY blocks registers
8 - #phy-cells:
9 - Must be 1 for brcm,sr-usb-combo-phy as it expects one argument to indicate
10 the PHY number of two PHYs. 0 for HS PHY and 1 for SS PHY.
11 - Must be 0 for brcm,sr-usb-hs-phy.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties
16 usbphy0: usb-phy@0 {
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| D | brcm-sata-phy.txt | 1 * Broadcom SATA3 PHY
5 "brcm,bcm7216-sata-phy"
6 "brcm,bcm7425-sata-phy"
7 "brcm,bcm7445-sata-phy"
8 "brcm,iproc-ns2-sata-phy"
9 "brcm,iproc-nsp-sata-phy"
10 "brcm,phy-sata3"
11 "brcm,iproc-sr-sata-phy"
12 "brcm,bcm63138-sata-phy"
15 - reg: register ranges for the PHY PCB interface
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| D | phy-bindings.txt | 2 information about PHY subsystem refer to Documentation/driver-api/phy/phy.rst
4 PHY device node
8 #phy-cells: Number of cells in a PHY specifier; The meaning of all those
9 cells is defined by the binding for the phy node. The PHY
11 PHY.
14 phy-supply: Phandle to a regulator that provides power to the PHY. This
15 regulator will be managed during the PHY power on/off sequence.
19 phys: phy {
24 #phy-cells = <1>;
29 That node describes an IP block (PHY provider) that implements 2 different PHYs.
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| D | phy-hisi-inno-usb2.txt | 1 Device tree bindings for HiSilicon INNO USB2 PHY
5 "hisilicon,inno-usb2-phy",
6 "hisilicon,hi3798cv200-usb2-phy".
7 - reg: Should be the address space for PHY configuration register in peripheral
9 - clocks: The phandle and clock specifier pair for INNO USB2 PHY device
11 - resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
16 The INNO USB2 PHY device should be a child node of peripheral controller that
17 contains the PHY configuration register, and each device suppports up to 2 PHY
18 ports which are represented as child nodes of INNO USB2 PHY device.
20 Required properties for PHY port node:
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| D | phy-stm32-usbphyc.txt | 1 STMicroelectronics STM32 USB HS PHY controller
3 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
4 switch. It controls PHY configuration and status, and the UTMI+ switch that
5 selects either OTG or HOST controller for the second PHY port. It also sets
11 |_ PHY port#1 _________________ HOST controller
14 |_ PHY port#2 ----| |________________
19 Phy provider node
24 - reg: address and length of the usb phy control register set
25 - clocks: phandle + clock specifier for the PLL phy clock
30 - assigned-clocks: phandle + clock specifier for the PLL phy clock
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| D | allwinner,sun9i-a80-usb-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/allwinner,sun9i-a80-usb-phy.yaml#
7 title: Allwinner A80 USB PHY Device Tree Bindings
14 "#phy-cells":
18 const: allwinner,sun9i-a80-usb-phy
25 - description: Main PHY Clock
28 - description: Main PHY clock
34 - const: phy
37 - const: phy
43 - description: Normal USB PHY reset
46 - description: Normal USB PHY reset
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| D | brcm,cygnus-pcie-phy.txt | 1 Broadcom Cygnus PCIe PHY
4 - compatible: must be "brcm,cygnus-pcie-phy"
5 - reg: base address and length of the PCIe PHY block
9 Each PCIe PHY should be represented by a child node
12 - reg: the PHY ID
15 - #phy-cells: must be 0
18 pcie_phy: phy@301d0a0 {
19 compatible = "brcm,cygnus-pcie-phy";
22 pcie0_phy: phy@0 {
24 #phy-cells = <0>;
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| D | ti-phy.txt | 1 TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
3 OMAP CONTROL PHY
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
11 e.g. USB3 PHY and SATA PHY on OMAP5.
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
14 e.g. PCIE PHY in DRA7x
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
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| D | renesas,usb2-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/renesas,usb2-phy.yaml#
7 title: Renesas R-Car generation 3 USB 2.0 PHY
16 - const: renesas,usb2-phy-r8a77470 # RZ/G1C
20 - renesas,usb2-phy-r7s9210 # RZ/A2
21 - renesas,usb2-phy-r8a774a1 # RZ/G2M
22 - renesas,usb2-phy-r8a774b1 # RZ/G2N
23 - renesas,usb2-phy-r8a774c0 # RZ/G2E
24 - renesas,usb2-phy-r8a774e1 # RZ/G2H
25 - renesas,usb2-phy-r8a7795 # R-Car H3
26 - renesas,usb2-phy-r8a7796 # R-Car M3-W
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| D | lantiq,vrx200-pcie-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
7 title: Lantiq VRX200 and ARX300 PCIe PHY Device Tree Bindings
13 "#phy-cells":
15 description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
19 - lantiq,vrx200-pcie-phy
20 - lantiq,arx300-pcie-phy
27 - description: PHY module clock
32 - const: phy
37 - description: exclusive PHY reset line
38 - description: shared reset line between the PCIe PHY and PCIe controller
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| D | socionext,uniphier-usb2-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb2-phy.yaml#
7 title: Socionext UniPhier USB2 PHY
10 This describes the devicetree bindings for PHY interface built into
13 controller doesn't include its own High-Speed PHY. This needs to specify
14 USB2 PHY instead of USB3 HS-PHY.
22 - socionext,uniphier-pro4-usb2-phy
23 - socionext,uniphier-ld11-usb2-phy
32 "^phy@[0-9]+$":
41 The ID number for the PHY
43 "#phy-cells":
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| D | phy-cadence-torrent.yaml | 4 $id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
7 title: Cadence Torrent SD0801 PHY binding
10 This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
12 PHY also supports multilink multiprotocol combinations including protocols
22 - cdns,torrent-phy
34 PHY reference clock. Must contain an entry in clock-names.
43 - description: Offset of the Torrent PHY configuration registers.
44 - description: Offset of the DPTX PHY configuration registers.
57 - description: Torrent PHY reset.
68 '^phy@[0-3]$':
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| D | brcm,bcm63xx-usbh-phy.yaml | 4 $id: "http://devicetree.org/schemas/phy/brcm,bcm63xx-usbh-phy.yaml#"
7 title: BCM63xx USBH PHY
15 - brcm,bcm6318-usbh-phy
16 - brcm,bcm6328-usbh-phy
17 - brcm,bcm6358-usbh-phy
18 - brcm,bcm6362-usbh-phy
19 - brcm,bcm6368-usbh-phy
20 - brcm,bcm63268-usbh-phy
39 "#phy-cells":
50 - "#phy-cells"
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| D | amlogic,meson8b-usb2-phy.yaml | 4 $id: "http://devicetree.org/schemas/phy/amlogic,meson8b-usb2-phy.yaml#"
7 title: Amlogic Meson8, Meson8b, Meson8m2 and GXBB USB2 PHY
17 - amlogic,meson8-usb2-phy
18 - amlogic,meson8b-usb2-phy
19 - amlogic,meson8m2-usb2-phy
20 - const: amlogic,meson-mx-usb2-phy
21 - const: amlogic,meson-gxbb-usb2-phy
37 "#phy-cells":
40 phy-supply:
42 Phandle to a regulator that provides power to the PHY. This
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| D | rockchip-usb-phy.txt | 1 ROCKCHIP USB2 PHY
5 "rockchip,rk3066a-usb-phy"
6 "rockchip,rk3188-usb-phy"
7 "rockchip,rk3288-usb-phy"
13 register files" - phy should be a child of the GRF instead
16 Each PHY should be represented as a sub-node.
20 - #phy-cells: should be 0
21 - reg: PHY configure reg address offset in GRF
22 "0x320" - for PHY attach to OTG controller
23 "0x334" - for PHY attach to HOST0 controller
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| D | qcom,qmp-usb3-dp-phy.yaml | 5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
8 title: Qualcomm QMP USB3 DP PHY controller
16 - qcom,sc7180-qmp-usb3-dp-phy
17 - qcom,sc7180-qmp-usb3-phy
18 - qcom,sdm845-qmp-usb3-dp-phy
19 - qcom,sdm845-qmp-usb3-phy
22 - description: Address and length of PHY's USB serdes block.
24 - description: Address and length of PHY's DP serdes block.
45 - description: Phy aux clock.
46 - description: Phy config clock.
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| D | qcom,qusb2-phy.yaml | 5 $id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"
8 title: Qualcomm QUSB2 phy controller
21 - qcom,ipq8074-qusb2-phy
22 - qcom,msm8996-qusb2-phy
23 - qcom,msm8998-qusb2-phy
26 - qcom,sc7180-qusb2-phy
27 - qcom,sdm845-qusb2-phy
28 - const: qcom,qusb2-v2-phy
32 "#phy-cells":
39 - description: phy config clock
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| D | brcm,brcmstb-usb-phy.txt | 1 Broadcom STB USB PHY
5 "brcm,brcmstb-usb-phy"
6 "brcm,bcm7216-usb-phy"
7 "brcm,bcm7211-usb-phy"
11 "brcm,brcmstb-usb-phy":
15 "brcm,bcm7216-usb-phy":
19 "brcm,bcm7211-usb-phy":
25 - #phy-cells: Shall be 1 as it expects one argument for setting
26 the type of the PHY. Possible values are:
27 - PHY_TYPE_USB2 for USB1.1/2.0 PHY
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| D | meson-gxl-usb2-phy.txt | 1 * Amlogic Meson GXL and GXM USB2 PHY binding
4 - compatible: Should be "amlogic,meson-gxl-usb2-phy"
6 - #phys-cells: must be 0 (see phy-bindings.txt in this directory)
9 - clocks: a phandle to the clock of this PHY
10 - clock-names: must be "phy"
11 - resets: a phandle to the reset line of this PHY
12 - reset-names: must be "phy"
13 - phy-supply: see phy-bindings.txt in this directory
17 usb2_phy0: phy@78000 {
18 compatible = "amlogic,meson-gxl-usb2-phy";
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| D | qcom-pcie2-phy.txt | 1 Qualcomm PCIe2 PHY controller
4 The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
9 "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"
11 - reg: offset and length of the PHY register set.
12 - #phy-cells: must be 0.
19 - resets: reset-specifier pairs for the "phy" and "pipe" resets
21 "phy" and "pipe"
23 - clock-output-names: name of the outgoing clock signal from the PHY PLL
27 phy@7786000 {
28 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
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| /Documentation/devicetree/bindings/ufs/ |
| D | ufs-qcom.txt | 1 * Qualcomm Technologies Inc Universal Flash Storage (UFS) PHY
3 UFSPHY nodes are defined to describe on-chip UFS PHY hardware macro.
4 Each UFS PHY node should have its own node.
6 To bind UFS PHY with UFS host controller, the controller node should
7 contain a phandle reference to UFS PHY node.
11 "qcom,ufs-phy-qmp-20nm" for 20nm ufs phy,
12 "qcom,ufs-phy-qmp-14nm" for legacy 14nm ufs phy,
13 "qcom,msm8996-ufs-phy-qmp-14nm" for 14nm ufs phy
15 - reg : should contain PHY register address space (mandatory),
18 - #phy-cells : This property shall be set to 0
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| /Documentation/devicetree/bindings/net/ |
| D | fsl-fec.txt | 7 - phy-mode : See ethernet.txt file in the same directory
10 - phy-supply : regulator that powers the Ethernet PHY.
11 - phy-handle : phandle to the PHY device connected to this device.
13 Use instead of phy-handle.
44 - mdio : specifies the mdio bus in the FEC, used as a container for phy nodes
45 according to phy.txt in the same directory
48 To avoid these, create a phy node according to phy.txt in the same
49 directory, and point the fec's "phy-handle" property to it. Then use
50 the phy's reset binding, again described by phy.txt.
51 - phy-reset-gpios : Should specify the gpio for phy reset
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