Searched full:phys (Results 1 – 25 of 192) sorted by relevance
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| /Documentation/devicetree/bindings/phy/ |
| D | phy-bindings.txt | 19 phys: phy {
29 That node describes an IP block (PHY provider) that implements 2 different PHYs.
30 In order to differentiate between these 2 PHYs, an additional specifier should be
37 phys : the phandle for the PHY device (used by the PHY subsystem; not to be
40 phy-names : the names of the PHY corresponding to the PHYs present in the
41 *phys* phandle
49 phys = <&usb2_phy>, <&usb3_phy>;
55 This node represents a controller that uses two PHYs, one for usb2 and one for
64 phys = <&phys 1>;
70 This node represents a controller that uses one of the PHYs of the PHY provider
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| D | calxeda-combophy.yaml | 7 title: Calxeda Highbank Combination PHYs binding for SATA
10 The Calxeda Combination PHYs connect the SoC to the internal fabric
11 and to SATA connectors. The PHYs support multiple protocols (SATA,
14 Programming the PHYs is typically handled by those device drivers,
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| D | amlogic,meson-axg-pcie.yaml | 22 phys:
34 - phys
49 phys = <&mipi_analog_phy PHY_TYPE_PCIE>;
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| D | pxa1928-usb-phy.txt | 1 * Marvell PXA1928 USB and HSIC PHYs
7 - #phys-cells: should be 0. From commmon phy binding.
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| /Documentation/devicetree/bindings/ata/ |
| D | marvell.txt | 10 - phys : List of phandles to sata phys
19 phys = <&sata_phy0>, <&sata_phy1>;
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| D | ahci-platform.txt | 8 PHYs.
34 - phys : reference to the SATA PHY node
49 - phys : reference to the SATA PHY node
70 phys = <&sata_phy 0>;
76 phys = <&sata_phy 1>;
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| D | exynos-sata.txt | 11 - phys : Must contain exactly one entry as specified
28 phys = <&sata_phy>;
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| /Documentation/devicetree/bindings/net/ |
| D | micrel.txt | 3 These properties cover the base properties Micrel PHYs.
7 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
9 Configure the LED mode with single value. The list of PHYs and the
41 Some PHYs, such as the KSZ8041FTL variant, support fiber mode, enabled
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| D | hisilicon-hns-nic.txt | 11 connect to 8 PHYs. Port 0 to 1 are both used for administration purpose. They
14 The remaining 6 PHYs are taken according to the mode of DSAF.
16 In NIC mode of DSAF, all 6 PHYs are taken as ethernet ports to the CPU. The
26 In Switch mode of DSAF, all 6 PHYs are taken as physical ports connect to a
43 In NIC mode of DSAF, all 6 PHYs of service DSAF are taken as ethernet ports
53 In Switch mode of DSAF, all 6 PHYs of service DSAF are taken as physical
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| D | cpsw.txt | 26 (DEPRECATED, use phys property instead).
48 - phys : phandle on phy-gmii-sel PHY (see phy/ti-phy-gmii-sel.txt)
92 phys = <&phy_gmii_sel 1 0>;
99 phys = <&phy_gmii_sel 2 0>;
123 phys = <&phy_gmii_sel 1 0>;
130 phys = <&phy_gmii_sel 2 0>;
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| /Documentation/devicetree/bindings/usb/ |
| D | brcm,bdc.txt | 16 - phys: phandle to one or two USB PHY blocks
18 USB 2.0 and USB 3.0 phys
27 phys = <&usbphy_0 0x0>;
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| D | brcm,bcm7445-ehci.yaml | 32 phys:
42 - phys
53 phys = <&usbphy_0 0x0>;
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| D | marvell,pxau2o-ehci.yaml | 32 phys:
44 - phys
58 phys = <&usb_otg_phy>;
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| D | ingenic,musb.yaml | 42 phys:
55 - phys
78 phys = <&usb_phy>;
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| D | amlogic,meson-g12a-usb-ctrl.yaml | 18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
68 phys:
96 - phys
210 phys = <&usb2_phy0>, <&usb2_phy1>, <&usb3_phy0>;
219 phys = <&usb2_phy1>;
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| D | ohci-da8xx.txt | 8 - phys: Phandle for the PHY device
20 phys = <&usb_phy 1>;
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| D | usb.yaml | 18 phys:
21 List of all the USB PHYs on this HCD
30 List of all the USB PHYs on this HCD to be accepted by the legacy USB
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| D | iproc-udc.txt | 14 - phys: phandle to phy node.
21 phys = <&usbdrd_phy>;
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| D | allwinner,sun4i-a10-musb.yaml | 41 phys:
66 - phys
94 phys = <&usbphy 0>;
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| D | ehci-omap.txt | 14 - phys: list of phandles to PHY nodes.
30 phys = <&hsusb1_phy 0 &hsusb3_phy>;
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| /Documentation/devicetree/bindings/pci/ |
| D | pci-armada8k.txt | 21 - phys: phandle(s) to PHY node(s) following the generic PHY bindings.
22 Either 1, 2 or 4 PHYs might be needed depending on the number of
24 - phy-names: names of the PHYs corresponding to the number of lanes.
26 2 PHYs.
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| D | pci.txt | 48 document, it is a five-cell address encoded as (phys.hi phys.mid
49 phys.lo size.hi size.lo). phys.hi should contain the device's BDF as
60 above this port, then phys.hi contains the 8-bit function number as
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| D | pci-keystone.txt | 63 phys: phandle to generic Keystone SerDes PHY for PCI
65 - If boot loader already does PCI link establishment, then phys and
71 1. pcie_bus clock-names not used. Instead, a phandle to phys is used.
97 phys: list of PHY specifiers (used by generic PHY framework)
100 ("phys" and "phy-names" DT bindings are specified in
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| /Documentation/devicetree/bindings/virtio/ |
| D | iommu.txt | 14 address encoded as (phys.hi phys.mid phys.lo size.hi
15 size.lo). phys.hi should contain the device's BDF as
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| /Documentation/driver-api/phy/ |
| D | samsung-usb2.rst | 43 const struct samsung_usb2_common_phy *phys;
49 The num_phys is the number of phys handled by the driver. `*phys` is an
61 .phys = exynos4210_phys,
130 phys are available - device, host, HSCI0 and HSCI1.
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