| /Documentation/devicetree/bindings/pinctrl/ |
| D | intel,lgm-io.yaml | 7 title: Intel Lightning Mountain SoC pinmux & GPIO controller binding
13 Pinmux & GPIO controller controls pin multiplexing & configuration including
30 $ref: pinmux-node.yaml#
36 pinmux: true
57 # Pinmux controller node
67 pinmux = <1>,
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| D | nvidia,tegra194-pinmux.txt | 1 NVIDIA Tegra194 pinmux controller
4 - compatible: "nvidia,tegra194-pinmux"
7 - second entry: The PINMUX_AUX_* registers (pinmux)
60 These correspond to Tegra PADCTL_* (pinmux) registers.
64 These correspond to Tegra PADCTL_* (pinmux) registers. Any property
72 See the list above for the pin name to use when configuring the pinmux.
88 tegra_pinctrl: pinmux: pinmux@2430000 {
89 compatible = "nvidia,tegra194-pinmux";
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| D | pinctrl-zx.txt | 17 | pinmux |
23 | pinmux | |
24 | pinmux v |
36 For most of pins like GMII_RXD3 in the figure, the pinmux function is
38 'TOP pins'. For pins like KEY_ROW2, the pinmux is controlled by both
41 Though pinmux implementation is quite different, pinconf is same for both
49 implements pinmux for AON pins and pinconf for all pins.
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| D | brcm,bcm4708-pinmux.txt | 10 Node of the pinmux must be nested in the CRU (Central Resource Unit) "syscon"
15 "brcm,bcm4708-pinmux"
16 "brcm,bcm4709-pinmux"
17 "brcm,bcm53012-pinmux"
46 compatible = "brcm,bcm4708-pinmux";
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| D | pinmux-node.yaml | 4 $id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml#
85 For cases like this, the pin controller driver may use the pinmux helper
87 in a pinmux group. A pinmux group consists of the pin identifier and mux
90 The pinmux property accepts an array of pinmux groups, each of them describing
95 pinmux = <PINMUX_GROUP>, <PINMUX_GROUP>, ...;
101 together in a pinmux group.
122 this, "pins" or "pinmux" has to be specified)
124 pinmux:
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| D | nvidia,tegra124-pinmux.txt | 1 NVIDIA Tegra124 pinmux controller
4 pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
5 nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
9 - compatible: For Tegra124, must contain "nvidia,tegra124-pinmux". For
10 Tegra132, must contain '"nvidia,tegra132-pinmux", "nvidia-tegra124-pinmux"'.
13 -- second entry - the pinmux registers
116 pinmux: pinmux {
117 compatible = "nvidia,tegra124-pinmux";
123 Example pinmux entries:
126 sdmmc4_default: pinmux {
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| D | pinctrl-mt65xx.txt | 16 - pins-are-numbered: Specify the subnodes are using numbered pinmux to
52 pinmux = <PIN_NUMBER_PINMUX>;
57 - pinmux: integer array, represents gpio pin number and mux setting.
106 pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
114 pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
122 pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
127 pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
134 pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
140 pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
147 pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
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| D | renesas,rzn1-pinctrl.yaml | 45 - $ref: pinmux-node.yaml#
53 pinmux:
62 same argument list of a single "pinmux" property.
63 Integers values in the "pinmux" argument list are assembled as:
85 - pinmux
112 pinmux = <
122 pinmux = <RZN1_PINMUX(103, RZN1_FUNC_UART0_I)>;
125 pinmux = <RZN1_PINMUX(104, RZN1_FUNC_UART0_I)>;
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| D | nvidia,tegra114-pinmux.txt | 1 NVIDIA Tegra114 pinmux controller
4 pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
5 nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
9 - compatible: "nvidia,tegra114-pinmux"
13 be pinmux register address.
96 pinmux: pinmux {
97 compatible = "nvidia,tegra114-pinmux";
99 0x70003000 0x40c>; /* PinMux registers */
105 sdmmc4_default: pinmux {
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| D | xlnx,zynq-pinctrl.txt | 18 Each configuration node can consist of multiple nodes describing the pinmux and
19 pinconf options. Those nodes can be pinmux nodes or pinconf nodes.
24 Required properties for pinmux nodes are:
25 - groups: A list of pinmux groups.
26 - function: The name of a pinmux function to activate for the specified set
32 - groups: A list of pinmux groups.
35 to specify in a pinmux subnode:
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| D | atmel,at91-pio4-pinctrl.txt | 28 pinmux = <PIN_NUMBER_PINMUX>;
33 - pinmux: integer array. Each integer represents a pin number plus mux and
64 pinmux = <PIN_PD21__TWD0>,
70 pinmux = <PIN_PB0>,
78 pinmux = <PIN_PA28__SDMMC1_CMD>,
87 pinmux = <PIN_PA22__SDMMC1_CK>,
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| D | brcm,nsp-pinmux.txt | 8 Must be "brcm,nsp-pinmux"
26 pinmux: pinmux@1803f1c0 {
27 compatible = "brcm,nsp-pinmux";
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| D | pinctrl-single.txt | 13 - pinctrl-single,register-width : pinmux register access width in bits
15 - pinctrl-single,function-mask : mask of allowed pinmux function bits
16 in the pinmux register
28 drive strength in the pinmux register. They're value of drive strength
35 input bias pullup in the pinmux register.
41 input bias pulldown in the pinmux register.
57 input schmitt in the pinmux register. In some silicons, there're two input
58 schmitt value (rising-edge & falling-edge) in the pinmux register.
64 configure input schmitt enable or disable in the pinmux register.
125 Optional sub-node: In case some pins could be configured as GPIO in the pinmux
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| D | renesas,rza1-ports.yaml | 70 - $ref: pinmux-node.yaml#
90 pinmux:
99 same argument list of a single "pinmux" property.
104 Integers values in "pinmux" argument list are assembled as:
112 - pinmux
150 pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;
162 pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>;
176 pinmux = <RZA1_PINMUX(4, 0, 2)>;
186 pinmux = <RZA1_PINMUX(4, 1, 1)>;
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| D | pinctrl_spear.txt | 1 ST Microelectronics, SPEAr pinmux controller
4 - compatible : "st,spear300-pinmux"
5 : "st,spear310-pinmux"
6 : "st,spear320-pinmux"
7 : "st,spear1310-pinmux"
8 : "st,spear1340-pinmux"
10 - st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
35 SPEAr's pinmux nodes act as a container for an arbitrary number of subnodes. Each
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| D | renesas,rza2-pinctrl.yaml | 47 - $ref: pinmux-node.yaml#
54 The values for the pinmux properties are a combination of port name,
64 pinmux:
71 - pinmux
97 pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */
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| D | nvidia,tegra124-dpaux-padctl.txt | 17 Child nodes contain the pinmux configurations following the conventions
36 state_dpaux_aux: pinmux-aux {
41 state_dpaux_i2c: pinmux-i2c {
46 state_dpaux_off: pinmux-off {
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| D | brcm,cygnus-pinmux.txt | 9 Must be "brcm,cygnus-pinmux"
28 pinmux: pinmux@0301d0c8 {
29 compatible = "brcm,cygnus-pinmux";
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| D | pinctrl-mt8192.yaml | 66 pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
70 pinmux = <PINMUX_GPIO1__FUNC_PWM_1>;
73 $ref: "pinmux-node.yaml"
76 pinmux:
107 - pinmux
152 pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
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| D | nvidia,tegra210-pinmux.txt | 1 NVIDIA Tegra210 pinmux controller
4 - compatible: "nvidia,tegra210-pinmux"
7 - second entry: The PINMUX_AUX_* registers (pinmux)
83 These correspond to Tegra PINMUX_AUX_* (pinmux) registers. Any property
129 use when configuring the pinmux.
146 pinmux: pinmux@70000800 {
147 compatible = "nvidia,tegra210-pinmux";
154 state_boot: pinmux {
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| D | bitmain,bm1880-pinctrl.txt | 17 includes pinmux and various pin configuration parameters, such as pull-up,
20 Each configuration node can consist of multiple nodes describing the pinmux
25 to specify in a pinmux subnode:
66 pinmux functions. The following are the list of pinmux
121 pinmux {
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| D | st,stm32-pinctrl.yaml | 124 pinmux:
142 To simplify the usage, macro is available to generate "pinmux" field.
148 pinmux = <STM32_PINMUX('A', 9, AF2)>;
152 pinmux = <STM32_PINMUX('A', 9, GPIO)>;
156 pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
183 - pinmux
251 pinmux = <STM32_PINMUX('A', 9, AF7)>;
257 pinmux = <STM32_PINMUX('A', 10, AF7)>;
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| D | meson,pinctrl.txt | 1 == Amlogic Meson pinmux controller ==
38 configuration for a pin or a group. Those nodes can be pinmux nodes or
41 Required properties for pinmux nodes are:
42 - groups: a list of pinmux groups. The list of all available groups
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| D | pinctrl-rk805.txt | 9 Optional Pinmux properties:
34 Following are optional properties defined as pinmux DT binding document
56 rk805_default: pinmux {
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| D | fsl,mxs-pinctrl.txt | 42 - fsl,pinmux-ids: An integer array. Each integer in the array specify a pin
87 fsl,pinmux-ids = <
106 fsl,pinmux-ids = <MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT>;
111 fsl,pinmux-ids = <MX28_PAD_SSP0_SCK__SSP0_SCK>;
124 Valid values for i.MX28/i.MX23 pinmux-id are defined in
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