Searched full:pixel (Results 1 – 25 of 195) sorted by relevance
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| /Documentation/userspace-api/media/v4l/ |
| D | ext-ctrls-image-process.rst | 24 Data bus frequency. Together with the media bus pixel code, bus type
25 (clock cycles per sample), the data bus frequency defines the pixel
26 rate (``V4L2_CID_PIXEL_RATE``) in the pixel array (or possibly
28 be calculated from the pixel clock, image width and height and
29 horizontal and vertical blanking. While the pixel rate control may
30 be defined elsewhere than in the subdev containing the pixel array,
32 because only on the pixel array it can be assumed that the vertical
34 allowed in the pixel array. The selection of frame rate is performed
39 Pixel rate in the source pads of the subdev. This control is
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| D | fourcc.rst | 3 Guidelines for Video4Linux pixel format 4CCs
8 the pixel format, compression and colour space. The interpretation of the
23 2nd character: pixel order
30 3rd character: uncompressed bits-per-pixel 0--9, A--
32 4th character: compressed bits-per-pixel 0--9, A--
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| D | vidioc-enum-framesizes.rst | 30 that contains an index and pixel format and receives a frame width
37 and height in pixels) that the device supports for the given pixel
40 The supported pixel formats can be obtained by using the
101 - Width of the frame [pixel].
104 - Height of the frame [pixel].
118 - Minimum frame width [pixel].
121 - Maximum frame width [pixel].
124 - Frame width step size [pixel].
127 - Minimum frame height [pixel].
130 - Maximum frame height [pixel].
[all …]
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| D | pixfmt-intro.rst | 29 leftmost pixel of the topmost row. Following that is the pixel
31 pixels. Following the rightmost pixel of the row there may be zero or
32 more bytes of padding to guarantee that each row of pixel data has a
34 leftmost pixel of the second row from the top, and so on. The last row
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| D | pixfmt-y12i.rst | 15 This is a grey-scale image with a depth of 12 bits per pixel, but with
16 pixels from 2 sources interleaved and bit-packed. Each pixel is stored
28 interleaved pixel.
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| D | pixfmt-cnf4.rst | 9 Depth sensor confidence information as a 4 bits per pixel packed array
20 Bits 0-3 of byte n refer to confidence value of depth pixel 2*n,
21 bits 4-7 to confidence value of depth pixel 2*n+1.
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| D | vidioc-g-fbuf.rst | 103 the pixel in the top left corner of the framebuffer. [#f1]_
129 - The pixel format of the framebuffer.
151 undefined. See :ref:`pixfmt` for information on pixel formats.
171 ``width`` times bytes-per-pixel or a larger value required by the
304 output = framebuffer pixel * alpha + video pixel * (1 - alpha).
305 The actual alpha depth depends on the framebuffer pixel format.
309 images. The blend function is: output = (framebuffer pixel * alpha
310 + video pixel * (255 - alpha)) / 255. The alpha value is
320 framebuffer pixel * (1 - alpha) + video pixel * alpha. The actual
321 alpha depth depends on the framebuffer pixel format.
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| D | ext-ctrls-image-source.rst | 27 the pixel rate defined by ``V4L2_CID_PIXEL_RATE`` control in the
36 Analogue gain is gain affecting all colour components in the pixel
58 The unit cell consists of the whole area of the pixel, sensitive and
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| D | pixfmt-y8i.rst | 16 This is a grey-scale image with a depth of 8 bits per pixel, but with
17 pixels from 2 sources interleaved. Each pixel is stored in a 16-bit
18 word. E.g. the R200 RealSense camera stores pixel from the left sensor
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| D | pixfmt-z16.rst | 10 16-bit depth data with distance values at each pixel
16 This is a 16-bit format, representing depth data. Each pixel is a
18 can vary and has to be negotiated with the device separately. Each pixel
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| /Documentation/devicetree/bindings/display/armada/ |
| D | marvell,dove-lcd.txt | 13 "axiclk" - axi bus clock for pixel clock
14 "plldivider" - pll divider clock for pixel clock
15 "ext_ref_clk0" - external clock 0 for pixel clock
16 "ext_ref_clk1" - external clock 1 for pixel clock
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | mt9p031.txt | 3 The Aptina MT9P031 is a 1/2.5-inch CMOS active pixel digital image sensor with
14 - pixel-clock-frequency: Pixel clock frequency.
35 pixel-clock-frequency = <96000000>;
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| /Documentation/devicetree/bindings/media/ |
| D | fsl-pxp.txt | 1 Freescale Pixel Pipeline
4 The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
6 pixel conversion via lookup table. Different versions are present on various
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| /Documentation/fb/ |
| D | pxafb.rst | 33 Pixel clock in picoseconds
63 4 or 8 pixel monochrome single panel data
72 Double pixel clock. 1=>true, 0=>false
80 pixel clock polarity
112 bpp = 16 -- for YUV422 planar (1 pixel = 1 Y + 1/2 Cb + 1/2 Cr)
114 bpp = 12 -- for YUV420 planar (1 pixel = 1 Y + 1/4 Cb + 1/4 Cr)
123 with minimum bits per pixel, e.g. for YUV420, Cr component
124 for one pixel is actually 2-bits, it means the line length
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| D | internals.rst | 61 Each pixel is either black or white.
66 The whole pixel value is fed through a programmable lookup table that has one
67 color (including red, green, and blue intensities) for each possible pixel
73 The pixel value is broken up into red, green, and blue fields.
78 The pixel value is broken up into red, green, and blue fields, each of which
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| D | api.rst | 47 to be aware of the pixel storage format in order to write image data to the
97 set to 0. When the number of bits per pixel is smaller than 8, several pixels
108 set to 1. When the number of bits per pixel is smaller than 8, several pixels
124 Pixel values are encoded as indices into a colormap that stores red, green and
128 Each pixel value is stored in the number of bits reported by the variable
198 __u32 nonstd; /* != 0 Non standard pixel format */
208 __u32 pixclock; /* pixel clock in ps (pico seconds) */
268 Pixel values are bits_per_pixel wide and are split in non-overlapping red,
270 component in the pixel value are described by the fb_bitfield offset and
274 bits per pixel is not a multiple of 8, pixel values are padded to the next
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| /Documentation/driver-api/media/ |
| D | csi2.rst | 32 V4L2_CID_PIXEL_RATE is may be used by the receiver to obtain the pixel
43 .. list-table:: variables in pixel rate calculation
91 The media bus pixel codes document parallel formats. Should the pixel data be
92 transported over a serial bus, the media bus pixel code that describes a
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| D | camera-sensor.rst | 38 of cropping and scaling operations from the device's pixel array's size.
72 (analogue crop height + vertical blanking) / pixel rate
76 crop, use the full source image size, i.e. pixel array size.
80 pixel rate is specified by ``V4L2_CID_PIXEL_RATE`` in the same sub-device. The
87 The first entity in the linear pipeline is the pixel array. The pixel array may
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| /Documentation/devicetree/bindings/display/ |
| D | brcm,bcm2835-dpi.yaml | 22 - description: The pixel clock that feeds the pixelvalve
27 - const: pixel
53 clock-names = "core", "pixel";
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| D | cirrus,clps711x-fb.txt | 11 - bits-per-pixel: Bits per pixel.
30 bits-per-pixel = <4>;
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| D | brcm,bcm2835-hdmi.yaml | 26 - description: The pixel clock
31 - const: pixel
76 clock-names = "pixel", "hdmi";
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| D | brcm,bcm2835-dsi0.yaml | 31 - description: The DSI pixel clock
37 - const: pixel
75 clock-names = "phy", "escape", "pixel";
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| /Documentation/devicetree/bindings/clock/ |
| D | fsl,plldig.yaml | 7 title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding
15 which generate and offers pixel clocks to Display.
49 # Display PIXEL Clock node:
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| /Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,dpi.txt | 5 provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
15 - clock-names: must contain "pixel", "engine", and "pll"
32 clock-names = "pixel", "engine", "pll";
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| /Documentation/devicetree/bindings/display/imx/ |
| D | fsl,imx-fb.txt | 14 - bits-per-pixel: Bits per pixel
41 bits-per-pixel = <16>;
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