Home
last modified time | relevance | path

Searched full:processing (Results 1 – 25 of 320) sorted by relevance

12345678910>>...13

/Documentation/devicetree/bindings/firmware/
Dintel,ixp4xx-network-processing-engine.yaml5 $id: "http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processing-engine.yaml#"
8 title: Intel IXP4xx Network Processing Engine
14 On the IXP4xx SoCs, the Network Processing Engine (NPE) is a small
25 - const: intel,ixp4xx-network-processing-engine
42 compatible = "intel,ixp4xx-network-processing-engine";
/Documentation/gpu/
Dmeson.rst2 drm/meson AmLogic Meson Video Processing Unit
6 :doc: Video Processing Unit
8 Video Processing Unit
16 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
20 R |-------| |----| Processing | | | | |
33 Video Post Processing
37 :doc: Video Post Processing
/Documentation/devicetree/bindings/media/
Dti,vpe.yaml7 title: Texas Instruments DRA7x Video Processing Engine (VPE) Device Tree Bindings
13 The Video Processing Engine (VPE) is a key component for image post
14 processing applications. VPE consist of a single memory to memory
Drenesas,jpu.txt1 * Renesas JPEG Processing Unit
3 The JPEG processing unit (JPU) incorporates the JPEG codec with an encoding
Drenesas,vsp1.yaml7 title: Renesas VSP Video Processing Engine
13 The VSP is a video processing engine that supports up-/down-scaling, alpha
14 blending, color space conversion and various other image processing features.
Dti-am437x-vpfe.txt4 The Video Processing Front End (VPFE) is a key component for image capture
6 processing capability to connect RAW image-sensor modules and video decoders
/Documentation/userspace-api/media/v4l/
Ddev-subdev.rst50 sensors and image processing hardware implement identical functions,
102 the video sensor and the host image processing hardware.
356 sub-device for processing.
408 Inside subdevs, the order of image processing steps will always be from
424 pad for further processing.
450 .. _subdev-image-processing-crop:
452 .. kernel-figure:: subdev-image-processing-crop.svg
453 :alt: subdev-image-processing-crop.svg
456 **Figure 4.5. Image processing in subdevs: simple crop example**
467 .. _subdev-image-processing-scaling-multi-source:
[all …]
Dlibv4l-introduction.rst56 processing functions to improve webcam video quality. The video
57 processing is split in to 2 parts: libv4lconvert/control and
58 libv4lconvert/processing.
61 control the video processing functions made available by
62 libv4lconvert/processing. These controls are stored application wide
65 libv4lconvert/processing offers the actual video processing
Dv4l2-selection-flags.rst40 - The configuration must not be propagated to any further processing
42 inside the subdevice to all further processing steps.
Ddev-touch.rst18 Processing is required to analyse the raw data and produce input events. In
22 processing must be done on the host.
/Documentation/usb/
Dohci.rst30 to overhead in IRQ processing. When interrupt transfers are queued, those
32 work on while the OS is getting around to the relevant IRQ processing.
/Documentation/hid/
Dhid-sensor.rst52 - Individual sensor processing part (sensor drivers)
65 function will be called. So an accelerometer processing driver can register
68 The core driver provides a set of APIs which can be used by the processing
72 Individual sensor processing part (sensor drivers)
75 The processing driver will use an interface provided by the core driver to parse
85 Each processing driver can use this structure to set some callbacks.
115 A processing driver can look for some field of interest and check if it exists
/Documentation/admin-guide/media/
Dplatform-cardlist.rst50 rcar_jpu Renesas JPEG Processing Unit
60 sh_veu SuperH VEU mem2mem video processing
69 ti-vpe TI VPE (Video Processing Engine)
76 vsp1 Renesas VSP1 Video Processing Engine
Dipu3.rst6 Intel Image Processing Unit 3 (IPU3) Imaging Unit (ImgU) driver
14 This file documents the Intel IPU3 (3rd generation Image Processing Unit)
27 The Imaging Unit (ImgU) is responsible for processing images captured
77 Image processing using IPU3 ImgU requires tools such as raw2pnm [#f1]_, and
162 - Processing parameters
184 format), ImgU starts processing the buffer and produces the video output in YUV
190 video nodes should be enabled for IPU3 to start image processing.
216 Details on processing parameters specific to the IPU3 can be found in
243 larger bayer frame for further YUV processing than "VIDEO" mode to get high
261 Processing the image in raw Bayer format
[all …]
/Documentation/networking/
Dscaling.rst29 queues to distribute processing among CPUs. The NIC distributes packets by
82 processing takes place in receive interrupt handling, it is advantageous
93 interrupt processing forms a bottleneck. Spreading load between CPUs
115 interrupt handler, RPS selects the CPU to perform protocol processing
117 on the desired CPU’s backlog queue and waking up the CPU for processing.
141 RPS may enqueue packets for processing. For each received packet,
143 of the list. The indexed CPU is the target for processing the packet,
147 processing on the remote CPU, and any queued packets are then processed
186 RPS scales kernel receive processing across CPUs without introducing
254 kernel processing of packets to the CPU where the application thread
[all …]
/Documentation/devicetree/bindings/display/
Damlogic,meson-vpu.yaml17 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
21 R |-------| |----| Processing | | | | |
37 VPP: Video Post Processing
40 The Video Post Processing is in charge of the scaling and blending of the
/Documentation/ABI/testing/
Dsysfs-class-net-queues7 Receive Packet Steering packet processing flow for this
41 Transmit Packet Steering packet processing flow for this
51 into the Transmit Packet Steering packet processing flow for this
/Documentation/driver-api/
Dsync_file.rst19 driver that issued the fence is not using/processing the buffer anymore, so it
34 related to a buffer that the driver is processing or is going to process, so
36 dma_fence_signal(), when it has finished using (or processing) that buffer.
/Documentation/devicetree/bindings/input/touchscreen/
Dcyttsp.txt28 scanning/processing cycles when the chip is in active mode.
31 scanning/processing cycles when the chip is in low-power mode.
40 scanning/processing cycle).
/Documentation/devicetree/bindings/remoteproc/
Dingenic,vpu.yaml7 title: Ingenic Video Processing Unit bindings
10 Inside the Video Processing Unit (VPU) of the recent JZ47xx SoCs from
/Documentation/devicetree/bindings/arm/
Dmicrochip,sparx5.yaml17 features such as advanced TCAM-based VLAN and QoS processing
19 TCAM-based frame processing using versatile content aware processor
/Documentation/networking/devlink/
Ddevlink-trap.rst12 kernel (i.e., the CPU) for processing.
15 IGMP membership reports to the kernel for processing by the bridge module.
16 Without processing such packets, the bridge module could never populate its
25 The fundamental ability of sending certain packets to the kernel for processing
251 - Traps packets dropped during processing of ingress flow action drop
254 - Traps packets dropped during processing of egress flow action drop
402 - Traps packets sampled during processing of flow action sample (e.g., via
406 - Traps packets logged during processing of flow action trap (e.g., via
525 ACL processing
575 ACL processing
[all …]
/Documentation/userspace-api/media/cec/
Dcec-ioc-g-mode.rst63 processing them and the follower will have to implement those messages.
65 the passthrough mode. See :ref:`cec-core-processing` for details.
138 receive CEC messages for processing. If someone else is already
148 receive CEC messages for processing. In addition it will put the
198 Core message processing details:
202 .. _cec-core-processing:
204 .. flat-table:: Core Message Processing
/Documentation/driver-api/iio/
Dtriggered-buffers.rst57 function. It should do as little processing as possible, because it runs in
63 processing takes place here. It usually reads data from the device and
/Documentation/arm/
Dinterrupts.rst33 exclusive of each other - if you're processing one interrupt from the
35 finish processing before you can service the new interrupt. Eg, an
112 need to leave the hardware IRQ enabled while processing it, and queueing
113 further IRQ events should the IRQ happen again while processing. The

12345678910>>...13