Searched +full:remote +full:- +full:endpoint (Results 1 – 25 of 223) sorted by relevance
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| /Documentation/devicetree/bindings/sound/ |
| D | audio-graph-card.txt | 3 Audio Graph Card specifies audio DAI connections of SoC <-> codec.
8 see ${LINUX}/Documentation/devicetree/bindings/sound/simple-card.yaml
10 Below are same as Simple-Card.
12 - label
13 - widgets
14 - routing
15 - dai-format
16 - frame-master
17 - bitclock-master
18 - bitclock-inversion
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | maxim,max9286.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jacopo Mondi <jacopo+renesas@jmondi.org>
12 - Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
13 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 - Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
18 Serial Links (GMSL) and outputs them on a CSI-2 D-PHY port using up to 4 data
28 '#address-cells':
31 '#size-cells':
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| D | tvp5150.txt | 4 (and also SECAM in the TVP5151 case) video signals to either 8-bit 4:2:2 YUV
5 with discrete syncs or 8-bit ITU-R BT.656 with embedded syncs output formats.
9 - compatible: Value must be "ti,tvp5150".
10 - reg: I2C slave address.
14 - pdn-gpios: Phandle for the GPIO connected to the PDN pin, if any.
15 - reset-gpios: Phandle for the GPIO connected to the RESETB pin, if any.
19 Documentation/devicetree/bindings/media/video-interfaces.txt. The port nodes
23 --------------------------------------
26 Y-OUT src 2
29 port must be linked to an endpoint defined in [1]. The port/connector layout is
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| D | imi,rdacm2x-gmsl.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/media/i2c/imi,rdacm2x-gmsl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jacopo Mondi <jacopo+renesas@jmondi.org>
12 - Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
13 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 - Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
16 description: -|
17 The IMI D&D RDACM20 and RDACM21 are GMSL-compatible camera designed for
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| D | ov5640.txt | 1 * Omnivision OV5640 MIPI CSI-2 / parallel sensor
4 - compatible: should be "ovti,ov5640"
5 - clocks: reference to the xclk input clock.
6 - clock-names: should be "xclk".
7 - DOVDD-supply: Digital I/O voltage supply, 1.8 volts
8 - AVDD-supply: Analog voltage supply, 2.8 volts
9 - DVDD-supply: Digital core voltage supply, 1.5 volts
12 - reset-gpios: reference to the GPIO connected to the reset pin, if any.
14 - powerdown-gpios: reference to the GPIO connected to the powerdown pin,
16 - rotation: as defined in
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| /Documentation/devicetree/bindings/media/ |
| D | renesas,csi2.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car MIPI CSI-2 receiver
11 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
14 The R-Car CSI-2 receiver device provides MIPI CSI-2 capabilities for the
15 Renesas R-Car and RZ/G2 family of devices. It is used in conjunction with the
16 R-Car VIN module, which provides the video capture capabilities.
21 - enum:
22 - renesas,r8a774a1-csi2 # RZ/G2M
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| D | renesas,vin.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car Video Input (VIN)
11 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
14 The R-Car Video Input (VIN) device provides video input capabilities for the
15 Renesas R-Car family of devices.
20 on Gen3 and RZ/G2 platforms to a CSI-2 receiver.
25 - items:
26 - enum:
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| D | cdns,csi2rx.txt | 1 Cadence MIPI-CSI2 RX controller
4 The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
8 - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible
9 - reg: base address and size of the memory mapped region
10 - clocks: phandles to the clocks driving the controller
11 - clock-names: must contain:
14 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
18 - phys: phandle to the external D-PHY, phy-names must be provided
19 - phy-names: must contain "dphy", if the implementation uses an
20 external D-PHY
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| D | cdns,csi2tx.txt | 1 Cadence MIPI-CSI2 TX controller
4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
8 - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"
9 for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1
10 - reg: base address and size of the memory mapped region
11 - clocks: phandles to the clocks driving the controller
12 - clock-names: must contain:
15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
19 - phys: phandle to the D-PHY. If it is set, phy-names need to be set
20 - phy-names: must contain "dphy"
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| D | ti,da850-vpif.txt | 2 ----------------------
12 - compatible: must be "ti,da850-vpif"
13 - reg: physical base address and length of the registers set for the device;
14 - interrupts: should contain IRQ line for the VPIF
18 VPIF has a 16-bit parallel bus input, supporting 2 8-bit channels or a
19 single 16-bit channel. It should contain one or two port child nodes
20 with child 'endpoint' node. If there are two ports then port@0 must
23 Documentation/devicetree/bindings/media/video-interfaces.txt.
25 Example using 2 8-bit input channels, one of which is connected to an
26 I2C-connected TVP5147 decoder:
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| D | video-mux.txt | 7 the bindings in Documentation/devicetree/bindings/mux/mux-controller.txt
10 - compatible : should be "video-mux"
11 - mux-controls : mux controller node to use for operating the mux
12 - #address-cells: should be <1>
13 - #size-cells: should be <0>
14 - port@*: at least three port nodes containing endpoints connecting to the
18 Optionally, #address-cells, #size-cells, and port nodes can be grouped under a
23 mux: mux-controller {
24 compatible = "gpio-mux";
25 #mux-control-cells = <0>;
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| /Documentation/devicetree/bindings/ |
| D | graph.txt | 4 ---------------
12 can not be inferred from device tree parent-child relationships. The device
22 Documentation/devicetree/bindings/media/video-interfaces.txt.
28 -----------------------------------
31 Each port node contains an 'endpoint' subnode for each remote device port
33 remote device, an 'endpoint' child node must be provided for each link.
35 endpoint at a port, or a port node needs to be associated with a selected
36 hardware interface, a common scheme using '#address-cells', '#size-cells'
41 #address-cells = <1>;
42 #size-cells = <0>;
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| /Documentation/devicetree/bindings/arm/ |
| D | coresight.txt | 11 * Required properties for all components *except* non-configurable replicators
12 and non-configurable funnels:
16 - Embedded Trace Buffer (version 1.0):
17 "arm,coresight-etb10", "arm,primecell";
19 - Trace Port Interface Unit:
20 "arm,coresight-tpiu", "arm,primecell";
22 - Trace Memory Controller, used for Embedded Trace Buffer(ETB),
26 "arm,coresight-tmc", "arm,primecell";
28 - Trace Programmable Funnel:
29 "arm,coresight-dynamic-funnel", "arm,primecell";
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| /Documentation/devicetree/bindings/display/ |
| D | allwinner,sun8i-r40-tcon-top.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-r40-tcon-top.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
22 / [0] TCON-LCD0
25 \ / [1] TCON-LCD1 - LCD1/LVDS1
26 TCON-TOP
27 / \ [2] TCON-TV0 [0] - TVE0/RGB
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| D | arm,hdlcd.txt | 9 - compatible: "arm,hdlcd"
10 - reg: Physical base address and length of the controller's registers.
11 - interrupts: One interrupt used by the display controller to notify the
14 - clocks: A list of phandle + clock-specifier pairs, one for each
15 entry in 'clock-names'.
16 - clock-names: A list of clock names. For HDLCD it should contain:
17 - "pxlclk" for the clock feeding the output PLL of the controller.
19 Required sub-nodes:
20 - port: The HDLCD connection to an encoder chip. The connection is modeled
25 - memory-region: phandle to a node describing memory (see
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | lontium,lt9611.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
18 - lontium,lt9611
23 "#sound-dai-cells":
29 reset-gpios:
33 vdd-supply:
36 vcc-supply:
43 "#address-cells":
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| D | toshiba,tc358775.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinay Simha BN <simhavcs@gmail.com>
15 MIPI DSI-RX Data 4-lane, CLK 1-lane with data rates up to 800 Mbps/lane.
17 Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
19 Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
30 vdd-supply:
34 vddio-supply:
38 stby-gpios:
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| D | toshiba,tc358762.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
18 - toshiba,tc358762
24 vddc-supply:
31 "#address-cells":
34 "#size-cells":
49 endpoint:
54 remote-endpoint: true
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| D | toshiba,tc358768.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Ujfalusi <peter.ujfalusi@ti.com>
18 - toshiba,tc358768
19 - toshiba,tc358778
25 reset-gpios:
29 vddc-supply:
32 vddmipi-supply:
35 vddio-supply:
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| D | renesas,dw-hdmi.txt | 9 following device-specific properties.
14 - compatible : Shall contain one or more of
15 - "renesas,r8a774a1-hdmi" for R8A774A1 (RZ/G2M) compatible HDMI TX
16 - "renesas,r8a774b1-hdmi" for R8A774B1 (RZ/G2N) compatible HDMI TX
17 - "renesas,r8a774e1-hdmi" for R8A774E1 (RZ/G2H) compatible HDMI TX
18 - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
19 - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
20 - "renesas,r8a77961-hdmi" for R8A77961 (R-Car M3-W+) compatible HDMI TX
21 - "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX
22 - "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 and RZ/G2 compatible
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| /Documentation/devicetree/bindings/display/ti/ |
| D | ti,omap-dss.txt | 5 -------------------
25 -----------
36 -------
39 name for each display. If no aliases are defined, a semi-random number is used
43 -------
45 A shortened example of the DSS description for OMAP4, with non-relevant parts
49 compatible = "ti,omap4-dss";
54 clock-names = "fck";
55 #address-cells = <1>;
56 #size-cells = <1>;
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| /Documentation/devicetree/bindings/display/rockchip/ |
| D | rockchip-lvds.txt | 5 - compatible: matching the soc type, one of
6 - "rockchip,rk3288-lvds";
7 - "rockchip,px30-lvds";
9 - reg: physical base address of the controller and length
11 - clocks: must include clock specifiers corresponding to entries in the
12 clock-names property.
13 - clock-names: must contain "pclk_lvds"
15 - avdd1v0-supply: regulator phandle for 1.0V analog power
16 - avdd1v8-supply: regulator phandle for 1.8V analog power
17 - avdd3v3-supply: regulator phandle for 3.3V analog power
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| D | dw_mipi_dsi_rockchip.txt | 5 - #address-cells: Should be <1>.
6 - #size-cells: Should be <0>.
7 - compatible: one of
8 "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"
9 "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"
10 "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"
11 - reg: Represent the physical address range of the controller.
12 - interrupts: Represent the controller's interrupt to the CPU(s).
13 - clocks, clock-names: Phandles to the controller's pll reference
17 - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
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| /Documentation/devicetree/bindings/media/xilinx/ |
| D | xlnx,csi2rxss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx MIPI CSI-2 Receiver Subsystem
10 - Vishal Sagar <vishal.sagar@xilinx.com>
13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
16 The subsystem consists of a MIPI D-PHY in slave mode which captures the
17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
21 Please note that this bindings includes only the MIPI CSI-2 Rx controller
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| /Documentation/devicetree/bindings/display/hisilicon/ |
| D | dw-dsi.txt | 1 Device-Tree bindings for DesignWare DSI Host Controller v1.20a driver
7 - compatible: value should be "hisilicon,hi6220-dsi".
8 - reg: physical base address and length of dsi controller's registers.
9 - clocks: contains APB clock phandle + clock-specifier pair.
10 - clock-names: should be "pclk".
11 - ports: contains DSI controller input and output sub port.
22 compatible = "hisilicon,hi6220-dsi";
25 clock-names = "pclk";
29 #address-cells = <1>;
30 #size-cells = <0>;
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