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/Documentation/devicetree/bindings/phy/
Dphy-hisi-inno-usb2.txt11 - resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
23 - resets: The phandle and reset specifier pair for PHY port reset signal.
40 resets = <&crg 0xbc 4>;
47 resets = <&crg 0xbc 8>;
53 resets = <&crg 0xbc 9>;
61 resets = <&crg 0xbc 6>;
68 resets = <&crg 0xbc 10>;
Dphy-cadence-torrent.yaml53 resets:
79 resets:
83 Contains list of resets, one per lane, to get all the link lanes out of reset.
121 - resets
136 - resets
154 resets = <&phyrst 0>;
162 resets = <&phyrst 1>, <&phyrst 2>,
183 resets = <&phyrst 0>, <&phyrst 1>;
191 resets = <&phyrst 2>, <&phyrst 3>;
200 resets = <&phyrst 4>;
Dqcom-pcie2-phy.txt19 - resets: reset-specifier pairs for the "phy" and "pipe" resets
20 - reset-names: list of resets, should contain:
32 resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
Dallwinner,sun9i-a80-usb-phy.yaml41 resets:
72 - resets
93 resets:
109 resets = <&usb_clocks RST_USB0_PHY>;
128 resets = <&usb_clocks RST_USB2_PHY>,
Dqcom,qmp-phy.yaml58 resets:
95 - resets
123 resets:
149 resets:
180 resets:
202 resets:
227 resets:
247 resets:
276 resets:
300 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
Dphy-cadence-sierra.txt7 - resets: Must contain an entry for each in reset-names.
37 - resets: Must contain one entry which controls the reset line for the
51 resets = <&phyrst 0>, <&phyrst 1>;
59 resets = <&phyrst 2>;
66 resets = <&phyrst 4>;
Damlogic,meson-axg-pcie.yaml19 resets:
36 - resets
48 resets = <&reset RESET_PCIE_PHY>;
Dallwinner,sun50i-h6-usb3-phy.yaml24 resets:
34 - resets
47 resets = <&ccu RST_USB_PHY1>;
Damlogic,g12a-usb3-pcie-phy.yaml28 resets:
43 - resets
56 resets = <&phy_reset>;
Dqcom-usb-ipq4019-phy.yaml21 resets:
35 - resets
49 resets = <&gcc USB2_HSPHY_POR_ARES>,
/Documentation/devicetree/bindings/fpga/
Daltera-hps2fpga-bridge.txt9 - resets : Phandle and reset specifier for this bridge's reset
18 resets = <&rst LWHPS2FPGA_RESET>;
26 resets = <&rst HPS2FPGA_RESET>;
34 resets = <&rst FPGA2HPS_RESET>;
/Documentation/devicetree/bindings/regulator/
Duniphier-regulator.txt10 the regulator, it is necessary to control the clocks and resets to enable
11 this layer. These clocks and resets should be described in each property.
26 - resets: A list of phandles to the reset control for USB3 glue layer.
27 According to the reset-names, appropriate resets are required.
50 resets = <&sys_rst 14>;
/Documentation/devicetree/bindings/display/
Dst,stih4xx.txt38 - resets: resets to be used by the device
40 - reset-names: names of the resets listed in resets property in the same
51 - resets: resets to be used by the device
53 - reset-names: names of the resets listed in resets property in the same
111 - resets: resets to be used by the device
113 - reset-names: names of the resets listed in resets property in the same
187 resets = <&softreset STIH416_COMPO_M_SOFTRESET>, <&softreset STIH416_COMPO_A_SOFTRESET>;
196 resets = <&softreset STIH416_HDTVOUT_SOFTRESET>;
236 resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
Dst,stm32-ltdc.yaml34 resets:
54 - resets
63 #include <dt-bindings/reset/stm32mp1-resets.h>
71 resets = <&rcc LTDC_R>;
/Documentation/devicetree/bindings/reset/
Duniphier-reset.txt8 this core reset, it is necessary to control the clocks and resets to enable
9 this layer. These clocks and resets should be described in each property.
28 - resets: A list of phandles to the reset control for the glue layer.
29 According to the reset-names, appropriate resets are required.
50 resets = <&sys_rst 14>;
Dxlnx,zynqmp-reset.txt4 The Zynq UltraScale+ MPSoC and Versal has several different resets.
7 about zynqmp resets.
42 <dt-bindings/reset/xlnx-zynqmp-resets.h>
44 <dt-bindings/reset/xlnx-versal-resets.h>
51 resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
Dimg,pistachio-reset.txt40 Device nodes should specify the reset channel required in their "resets"
49 resets = <&pistachio_reset PISTACHIO_RESET_SPDIF_OUT>;
54 Macro definitions for the supported resets can be found in:
55 include/dt-bindings/reset/pistachio-resets.h
/Documentation/devicetree/bindings/net/
Dmediatek,mt7620-gsw.txt10 - resets: Should contain the gigabit switches resets
19 resets = <&rstctrl 23>;
Dralink,rt3050-esw.txt11 - resets: Should contain the embedded switches resets
25 resets = <&rstctrl 23>;
/Documentation/devicetree/bindings/power/
Damlogic,meson-ee-pwrc.yaml45 resets:
83 - resets
108 - resets
126 - resets
151 - resets
169 resets = <&reset_viu>,
/Documentation/devicetree/bindings/media/
Dst,stm32-dcmi.yaml36 resets:
53 - resets
64 #include <dt-bindings/reset/stm32mp1-resets.h>
69 resets = <&rcc CAMITF_R>;
/Documentation/devicetree/bindings/i2c/
Dst,stm32-i2c.yaml65 resets:
94 - resets
111 resets = <&rcc 277>;
123 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
130 #include <dt-bindings/reset/stm32mp1-resets.h>
139 resets = <&rcc I2C2_R>;
/Documentation/devicetree/bindings/sound/
Damlogic,g12a-toacodec.yaml31 resets:
38 - resets
50 resets = <&clkc_audio AUD_RESET_TOACODEC>;
/Documentation/devicetree/bindings/crypto/
Dst,stm32-cryp.yaml27 resets:
42 #include <dt-bindings/reset/stm32mp1-resets.h>
48 resets = <&rcc CRYP1_R>;
/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra20-host1x.txt18 - resets: Must contain an entry for each entry in reset-names.
34 - resets: Must contain an entry for each entry in reset-names.
48 - resets: Must contain an entry for each entry in reset-names.
124 - resets: Must contain an entry for each entry in reset-names.
137 - resets: Must contain an entry for each entry in reset-names.
150 - resets: Must contain an entry for each entry in reset-names.
167 - resets: Must contain an entry for each entry in reset-names.
185 - resets: Must contain an entry for each entry in reset-names.
216 - resets: Must contain an entry for each entry in reset-names.
248 - resets: Must contain an entry for each entry in reset-names.
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