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/Documentation/driver-api/media/
Ddtv-core.rst8 - A bridge driver that is responsible to talk with the bus where the other
15 the hardware responsible for tuning into a digital TV transponder or
/Documentation/devicetree/bindings/power/reset/
Dmt6323-poweroff.txt3 The power controller which could be found on PMIC is responsible for externally
/Documentation/admin-guide/media/
Ddavinci-vpbe.rst27 When connected to an external encoder, vpbe controller is also responsible
38 Responsible for setting outputs provided through internal DACs and also
/Documentation/networking/
Dnfc.rst14 The NFC subsystem is responsible for:
19 The subsystem is divided in some parts. The 'core' is responsible for
21 responsible for providing an interface to control operations and low-level
Dtc-actions-env-rules.rst25 #) Thou art responsible for freeing anything returned as being
/Documentation/devicetree/bindings/sound/
Dsirf-audio-port.txt10 One of the DMA channels will be responsible for transmission (should be
Dbrcm,bcm2835-i2s.txt11 One of the DMA channels will be responsible for transmission (should be
Dsirf-usp.txt10 One of the DMA channels will be responsible for transmission (should be
Dux500-mop500.txt3 This node is responsible for linking together all ux500 Audio Driver components.
/Documentation/driver-api/soundwire/
Derror_handling.rst27 not be responsible for the errors so resetting them individually is not a
64 or Master driver implementers are responsible for writing valid values in
/Documentation/driver-api/
Dslimbus.rst31 A manager device is responsible for enumeration, configuration, and dynamic
36 Framer device is responsible for clocking the bus, and transmitting frame-sync
49 responsible to select the active-framer for clocking the bus.
/Documentation/networking/devlink/
Ddevlink-info.rst158 Control unit firmware version. This firmware is responsible for house
181 Version of the software responsible for supporting/handling the
193 RoCE firmware version which is responsible for handling roce
/Documentation/devicetree/bindings/reset/
Dbrcm,bcm7216-pcie-sata-rescal.yaml11 which is responsible for controlling the reset of the SATA and PCIe0/1
/Documentation/userspace-api/media/v4l/
Ddev-stateless-decoder.rst11 of any previous and future frames, and that the client is responsible for
21 cost of this simplicity is extra complexity in the client which is responsible
56 The client is responsible for making sure that these controls are set
200 is responsible for deducing the minimum number of buffers required
231 For each frame, the client is responsible for submitting at least one request to
375 for H.264) may have changed and the client is responsible for making sure that a
/Documentation/devicetree/bindings/arm/freescale/
Dfsl,imx7ulp-pm.yaml13 The Multi-System Mode Controller (MSMC) is responsible for sequencing
/Documentation/admin-guide/mm/
Dindex.rst5 Linux memory management subsystem is responsible, as the name implies,
/Documentation/devicetree/bindings/iio/
Dcommon.yaml19 document are defined as follows. The sensor tree bindings are responsible for
/Documentation/driver-api/acpi/
Dscan_handlers.rst59 that means that the handler has claimed the device node and is now responsible
61 be responsible for preparing the device node for unregistration in that case.
/Documentation/devicetree/bindings/ata/
Dpata-common.yaml18 The PATA (IDE) controller-specific device tree bindings are responsible for
Dsata-common.yaml18 The SATA controller-specific device tree bindings are responsible for
/Documentation/powerpc/
Dcxlflash.rst32 responsible for the initialization of the adapter, setting up the
205 This ioctl is responsible for transitioning the LUN to direct
222 This ioctl is responsible for transitioning the LUN to virtual mode
253 This ioctl is responsible for resizing a previously created virtual
272 This ioctl is responsible for releasing a previously obtained
285 This ioctl is responsible for unregistering a context with the
297 This ioctl is responsible for cloning a previously created
/Documentation/hwmon/
Dvexpress.rst29 chip/FPGA) a number of microcontrollers responsible for platform
/Documentation/devicetree/bindings/display/bridge/
Ddw_hdmi.txt11 responsible for defining whether each property is required or optional.
/Documentation/devicetree/bindings/clock/
Dnvidia,tegra210-car.txt6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
/Documentation/ABI/testing/
Dsysfs-class-net-qmi21 is responsible for coordination of driver and firmware

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