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/Documentation/admin-guide/blockdev/drbd/
Dnode-states-8.dot2 Secondary -> Primary [ label = "ioctl_set_state()" ]
3 Primary -> Secondary [ label = "ioctl_set_state()" ]
7 Secondary -> Primary [ label = "recv state packet" ]
8 Primary -> Secondary [ label = "recv state packet" ]
10 Secondary -> Unknown [ label = "connection lost" ]
12 Unknown -> Secondary [ label = "connected" ]
/Documentation/devicetree/bindings/powerpc/fsl/
Dpamu.txt63 - fsl,secondary-cache-geometry
65 Two cells that specify the geometry of the secondary PAMU
108 fsl,secondary-cache-geometry = <128 2>;
114 fsl,secondary-cache-geometry = <128 2>;
120 fsl,secondary-cache-geometry = <128 2>;
126 fsl,secondary-cache-geometry = <128 2>;
132 fsl,secondary-cache-geometry = <128 2>;
/Documentation/devicetree/bindings/interrupt-controller/
Dsnps,dw-apb-ictl.txt4 dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
15 Additional required property when it's used as secondary interrupt controller:
27 /* dw_apb_ictl is used as secondary interrupt controller */
Dmarvell,armada-8k-pic.txt4 This is the Device Tree binding for the PIC, a secondary interrupt
/Documentation/arm/samsung/
Dbootloader-interface.rst28 0x1c exynos4_secondary_startup Secondary CPU boot
29 0x1c + 4*cpu exynos4_secondary_startup (Exynos4412) Secondary CPU boot
44 0x00 exynos4_secondary_startup Secondary CPU boot
45 0x04 exynos4_secondary_startup (Exynos542x) Secondary CPU boot
46 4*cpu exynos4_secondary_startup (Exynos4412) Secondary CPU boot
60 0x0814 exynos4_secondary_startup (Exynos4210 r1.1) Secondary CPU boot
72 0x0908 Non-zero Secondary CPU boot up indicator
/Documentation/devicetree/bindings/arm/freescale/
Dfsl,layerscape-dcfg.txt4 configuration and status for the device. Such as setting the secondary
5 core start address and release the secondary core from holdoff and startup.
/Documentation/sparc/oradax/
Ddax-hv-api.txt172 [7:5] Secondary source address type
248 encoded data) and secondary data streams (meta-data for the encoded data).
260 … Variable width byte packed Data stream of lengths must be provided as a secondary
263 length encoding provided as a secondary input
267 as a secondary input
279 … a secondary input; pointer to the encoding table must be
291 … OZIP (CCB version 1) encoding as a secondary input; pointer to the encoding table must
296 … OZIP (CCB version 1) encoding stream of run lengths must be provided as a secondary
307 36.2.1.1.3. Secondary Input Format
309 …For primary input data streams which require a secondary input stream, the secondary input stream …
[all …]
/Documentation/devicetree/bindings/display/panel/
Dsharp,lq101r1sx01.yaml42 phandle to the DSI peripheral on the secondary link. Note that the
69 link2 = <&secondary>;
81 secondary: panel@0 {
/Documentation/devicetree/bindings/sound/
Dsamsung-i2s.yaml19 secondary FIFO, s/w reset control and internal mux for root clock
23 playback, stereo channel capture, secondary FIFO using internal
30 Exynos7 I2S has 7.1 channel TDM support for capture, secondary FIFO
111 subsystem (used in secondary sound source).
Dqcom,apq8016-sbc.txt33 * Secondary Mic
67 "MIC BIAS External1", "Secondary Mic",
86 /* External Primary or External Secondary -ADV7533 HDMI */
/Documentation/devicetree/bindings/arm/bcm/
Dbrcm,bcm63138.txt11 An optional Boot lookup table Device Tree node is required for secondary CPU
13 defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an
23 Optional properties for the secondary CPU node:
/Documentation/devicetree/bindings/arm/cpu-enable-method/
Dmarvell,berlin-smp2 Secondary CPU enable-method "marvell,berlin-smp" binding
5 This document describes the "marvell,berlin-smp" method for enabling secondary
Dal,alpine-smp2 Secondary CPU enable-method "al,alpine-smp" binding
6 enabling secondary CPUs. To apply to all CPUs, a single
/Documentation/hwmon/
Dibm-cffps.rst53 temp2_alarm Secondary rectifier temp over-temperature alarm.
54 temp2_input Measured secondary rectifier temp in millidegrees C.
Dnct6775.rst166 Secondary temperature source. Value is temperature
168 Set to 0 to disable secondary temperature control.
170 If secondary temperature functionality is enabled, it is controlled with the
182 Temperature at which secondary temperature control kicks
Dlm83.rst67 secondary chips coupled with another chip such as an IT8705F or similar
70 chips provide some temperature sensors, the secondary chip, if needed,
/Documentation/userspace-api/media/v4l/
Dvidioc-g-tuner.rst131 - receiving stereo audio and a secondary audio program
252 carrier and a secondary language monaural on a second carrier.
256 - Reception of the secondary language of a bilingual audio program
261 - Reception of a secondary audio program is supported. This is a
265 carrier for a monaural secondary language. Only
321 - The tuner receives the secondary language of a bilingual audio
368 - Play the secondary language, mono. When the tuner receives no
383 - Play the primary language on the left channel, the secondary
/Documentation/fb/
Dviafb.rst96 viafb_mode1: (secondary display device)
102 viafb_bpp1: (secondary display device)
105 viafb_refresh1: (secondary display device)
113 secondary device.
135 If CRT is primary and DVI is secondary, we should use::
139 If DVI is primary and CRT is secondary, we should use::
Dmatroxfb.rst231 with secondary (TV) output - if DFP is active, TV output must be
245 secondary analog output and third letter to the DVI output.
407 + secondary head shares videomemory with primary head. It is not problem
411 + due to hardware limitation, secondary head can use only 16 and 32bpp
413 + secondary head is not accelerated. There were bad problems with accelerated
414 XFree when secondary head used to use acceleration.
415 + secondary head always powerups in 640x480@60-32 videomode. You have to use
417 + secondary head always powerups in monitor mode. You have to use fbmatroxset
428 + secondary head shares videomemory with primary head. It is not problem
431 + due to hardware limitation, secondary head can use only 16 and 32bpp
[all …]
/Documentation/s390/
Dqeth.rst12 a primary or a secondary Bridge Port. For more information, see
24 ROLE={primary|secondary|none}
/Documentation/x86/
Dentry_64.rst60 So when we have a secondary entry, already in kernel mode, we *must
64 Now, there's a secondary complication: there's a cheap way to test
89 whether SWAPGS was already done: if we see that we are a secondary
/Documentation/devicetree/bindings/clock/
Dqcom,krait-cc.txt20 Definition: reference to the clock parents of hfpll, secondary muxes.
/Documentation/devicetree/bindings/power/supply/
Dtwl-charger.txt16 - interrupts: two interrupt lines from the TWL SIH (secondary
/Documentation/vm/
Dmmu_notifier.rst10 For secondary TLB (non CPU TLB) like IOMMU TLB or device TLB (when device use
13 those secondary TLB while holding page table lock when clearing a pte/pmd:
91 notification to invalidate the secondary TLB, the device see the new value for
/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-palmas.txt33 Selection primary or secondary function associated to I2C2_SCL_SCE,
36 Selection primary or secondary function associated to GPADC_START

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