Searched +full:sifive +full:- +full:blocks +full:- +full:ip +full:- +full:versioning (Results 1 – 5 of 5) sorted by relevance
| /Documentation/devicetree/bindings/sifive/ |
| D | sifive-blocks-ip-versioning.txt | 1 DT compatible string versioning for SiFive open-source IP blocks
4 strings for open-source SiFive IP blocks. HDL for these IP blocks
7 https://github.com/sifive/sifive-blocks
9 IP block-specific DT compatible strings are contained within the HDL,
10 in the form "sifive,<ip-block-name><integer version number>".
12 An example is "sifive,uart0" from:
14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
16 Until these IP blocks (or IP integration) support version
17 auto-discovery, the maintainers of these IP blocks intend to increment
19 interface to these IP blocks changes, or when the functionality of the
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| /Documentation/devicetree/bindings/pwm/ |
| D | pwm-sifive.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 SiFive, Inc.
4 ---
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive PWM controller
11 - Yash Shah <yash.shah@sifive.com>
12 - Sagar Kadam <sagar.kadam@sifive.com>
13 - Paul Walmsley <paul.walmsley@sifive.com>
16 Unlike most other PWM controllers, the SiFive PWM controller currently
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-sifive.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive SPI controller
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: "spi-controller.yaml#"
20 - const: sifive,fu540-c000-spi
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| /Documentation/devicetree/bindings/timer/ |
| D | sifive,clint.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive Core Local Interruptor
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-ocores.txt | 1 Device tree configuration for i2c-ocores
4 - compatible : "opencores,i2c-ocores"
6 "sifive,fu540-c000-i2c", "sifive,i2c0"
7 For Opencore based I2C IP block reimplemented in
8 FU540-C000 SoC. Please refer to sifive-blocks-ip-versioning.txt
10 - reg : bus address start and address range size of device
11 - clocks : handle to the controller clock; see the note below.
12 Mutually exclusive with opencores,ip-clock-frequency
13 - opencores,ip-clock-frequency: frequency of the controller clock in Hz;
15 - #address-cells : should be <1>
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