Searched +full:single +full:- +full:cell (Results 1 – 25 of 98) sorted by relevance
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| /Documentation/devicetree/bindings/i2c/ |
| D | nvidia,tegra186-bpmp-i2c.txt | 10 ../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
16 - compatible:
19 - "nvidia,tegra186-bpmp-i2c".
20 - #address-cells: Address cells for I2C device address.
21 Single-cell integer.
23 - #size-cells:
24 Single-cell integer.
26 - nvidia,bpmp-bus-id:
27 Single-cell integer.
37 compatible = "nvidia,tegra186-bpmp-i2c";
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | ti,c64x+megamod-pic.txt | 2 -------------------
8 Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
12 --------------------
13 - compatible: Should be "ti,c64x+core-pic";
14 - #interrupt-cells: <1>
17 ------------------------------
18 Single cell specifying the core interrupt priority level (4-15) where
22 -------
23 core_pic: interrupt-controller@0 {
24 interrupt-controller;
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| D | interrupts.txt | 5 -------------------------
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
20 interrupts are routed and contains a single phandle referring to the interrupt
25 The "interrupts-extended" property is a special form; useful when a node needs
31 interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
34 -----------------------------
36 A device is marked as an interrupt controller with the "interrupt-controller"
37 property. This is a empty, boolean property. An additional "#interrupt-cells"
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| D | arm,vic.txt | 5 nested or have the outputs wire-OR'd together.
9 - compatible : should be one of
10 "arm,pl190-vic"
11 "arm,pl192-vic"
12 - interrupt-controller : Identifies the node as an interrupt controller
13 - #interrupt-cells : The number of cells to define the interrupts. Must be 1 as
14 the VIC has no configuration options for interrupt sources. The cell is a u32
16 - reg : The register bank for the VIC.
20 - interrupts : Interrupt source for parent controllers if the VIC is nested.
21 - valid-mask : A one cell big bit mask of valid interrupt sources. Each bit
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| D | samsung,exynos4210-combiner.txt | 4 can combine interrupt sources as a group and provide a single interrupt request
13 A single node in the device tree is used to describe the interrupt combiner
16 combiners. For example, a 32-bit interrupt enable/disable config register
21 - compatible: should be "samsung,exynos4210-combiner".
22 - interrupt-controller: Identifies the node as an interrupt controller.
23 - #interrupt-cells: should be <2>. The meaning of the cells are
24 * First Cell: Combiner Group Number.
25 * Second Cell: Interrupt number within the group.
26 - reg: Base address and size of interrupt combiner registers.
27 - interrupts: The list of interrupts generated by the combiners which are then
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| D | arm,gic-v3.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
26 - qcom,msm8996-gic-v3
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| /Documentation/devicetree/bindings/iommu/ |
| D | iommu.txt | 13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
34 "dma-ranges" property that describes how the physical address space of the
35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a
39 --------------------
40 - #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
44 the specific IOMMU. Below are a few examples of typical use-cases:
46 - #iommu-cells = <0>: Single master IOMMU devices are not configurable and
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| D | msm,iommu-v0.txt | 5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
11 - interrupts: Specifiers for the MMU fault interrupts. For instances that
12 support secure mode two interrupts must be specified, for non-secure and
14 single interrupt must be specified.
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
18 - clocks : List of clocks to be used during SMMU register access. See
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
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| /Documentation/devicetree/bindings/spmi/ |
| D | qcom,spmi-pmic-arb.txt | 4 controller with wrapping arbitration logic to allow for multiple on-chip
5 devices to control a single SPMI master.
13 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
17 - compatible : should be "qcom,spmi-pmic-arb".
18 - reg-names : must contain:
19 "core" - core registers
20 "intr" - interrupt controller registers
21 "cnfg" - configuration registers
23 "chnls" - tx-channel per virtual slave registers.
24 "obsrvr" - rx-channel (called observer) per virtual slave registers.
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| /Documentation/devicetree/bindings/gpio/ |
| D | nvidia,tegra186-gpio.txt | 15 register set. These registers exist in a single contiguous block of physical
42 extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
43 describes the port-level mapping. In that file, the naming convention for ports
52 both the overall controller HW module and the sets-of-ports as "controllers".
56 interrupt signals generated by a set-of-ports. The intent is for each generated
59 per-port-set signals is reported via a separate register. Thus, a driver needs
66 - compatible
69 - "nvidia,tegra186-gpio".
70 - "nvidia,tegra186-gpio-aon".
71 - "nvidia,tegra194-gpio".
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| D | mediatek,mt7621-gpio.txt | 4 The registers of all the banks are interwoven inside one single IO range.
10 - #gpio-cells : Should be two. The first cell is the GPIO pin number and the
11 second cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>.
13 - #interrupt-cells : Specifies the number of cells needed to encode an
14 interrupt. Should be 2. The first cell defines the interrupt number,
16 Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
17 - compatible:
18 - "mediatek,mt7621-gpio" for Mediatek controllers
19 - reg : Physical base address and length of the controller's registers
20 - interrupt-parent : phandle of the parent interrupt controller.
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| D | gpio-sprd.txt | 3 The controller's registers are organized as sets of sixteen 16-bit
4 registers with each set controlling a bank of up to 16 pins. A single
8 - compatible: Should be "sprd,sc9860-gpio".
9 - reg: Define the base and range of the I/O address space containing
11 - gpio-controller: Marks the device node as a GPIO controller.
12 - #gpio-cells: Should be <2>. The first cell is the gpio number and
13 the second cell is used to specify optional parameters.
14 - interrupt-controller: Marks the device node as an interrupt controller.
15 - #interrupt-cells: Should be <2>. Specifies the number of cells needed
17 - interrupts: Should be the port interrupt shared by all the gpios.
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| D | wd,mbl-gpio.txt | 1 Bindings for the Western Digital's MyBook Live memory-mapped GPIO controllers.
3 The Western Digital MyBook Live has two memory-mapped GPIO controllers.
4 Both GPIO controller only have a single 8-bit data register, where GPIO
8 - compatible: should be "wd,mbl-gpio"
9 - reg-names: must contain
10 "dat" - data register
11 - reg: address + size pairs describing the GPIO register sets;
12 order must correspond with the order of entries in reg-names
13 - #gpio-cells: must be set to 2. The first cell is the pin number and
14 the second cell is used to specify the gpio polarity:
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| /Documentation/userspace-api/media/v4l/ |
| D | ext-ctrls-detect.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _detect-controls:
13 .. _detect-control-id:
28 .. flat-table::
29 :header-rows: 0
30 :stub-columns: 0
32 * - ``V4L2_DETECT_MD_MODE_DISABLED``
33 - Disable motion detection.
34 * - ``V4L2_DETECT_MD_MODE_GLOBAL``
35 - Use a single motion detection threshold.
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic.txt | 14 - compatible
22 - reg
24 Value type: <prop-encoded-array>
29 - interrupt-controller
35 - #interrupt-cells
39 specifiers do not contain the interrupt-type or type-specific
42 - #address-cells
47 - pic-no-reset
53 configuration registers to a sane state-- masked or
60 - big-endian
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| D | srio.txt | 5 - compatible
11 Optionally, a compatible string of "fsl,srio-vX.Y" where X is Major
15 - reg
17 Value type: <prop-encoded-array>
22 - interrupts
24 Value type: <prop_encoded-array>
30 A single IRQ that handles error conditions is specified by this
31 property. (Typically shared with port-write).
33 - fsl,srio-rmu-handle:
36 Definition: A single <phandle> value that points to the RMU.
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| /Documentation/devicetree/bindings/net/ |
| D | cavium-mix.txt | 4 - compatible: "cavium,octeon-5750-mix"
9 - reg: The base addresses of four separate register banks. The first
15 - cell-index: A single cell specifying which portion of the shared
18 - interrupts: Two interrupt specifiers. The first is the MIX
21 - phy-handle: Optional, see ethernet.txt file in the same directory.
25 compatible = "cavium,octeon-5750-mix";
30 cell-index = <1>;
32 local-mac-address = [ 00 0f b7 10 63 54 ];
33 phy-handle = <&phy1>;
|
| /Documentation/devicetree/bindings/clock/ |
| D | pistachio-clock.txt | 6 from the device-tree.
9 ----------------
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
18 ----------------------
21 co-processor), audio, and several peripherals.
24 - compatible: Must be "img,pistachio-clk".
25 - reg: Must contain the base address and length of the core clock controller.
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| /Documentation/devicetree/bindings/thermal/ |
| D | nvidia,tegra186-bpmp-thermal.txt | 9 ../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
11 This node represents a thermal sensor. See Documentation/devicetree/bindings/thermal/thermal-sensor…
15 - compatible:
18 - "nvidia,tegra186-bpmp-thermal"
19 - "nvidia,tegra194-bpmp-thermal"
20 - #thermal-sensor-cells: Cell for sensor index.
21 Single-cell integer.
30 compatible = "nvidia,tegra186-bpmp-thermal";
31 #thermal-sensor-cells = <1>;
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| /Documentation/devicetree/bindings/mfd/ |
| D | max77650.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MAX77650 ultra low-power PMIC from Maxim Integrated.
10 - Bartosz Golaszewski <bgolaszewski@baylibre.com>
13 MAX77650 is an ultra-low power PMIC providing battery charging and power
14 supply for low-power IoT and wearable applications.
16 The GPIO-controller module is represented as part of the top-level PMIC
17 node. The device exposes a single GPIO line.
19 For device-tree bindings of other sub-modules (regulator, power supply,
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| D | qcom-pm8xxx.txt | 1 Qualcomm PM8xxx PMIC multi-function devices
8 - compatible:
16 - #address-cells:
21 - #size-cells:
26 - interrupts:
28 Value type: <prop-encoded-array>
34 - #interrupt-cells:
38 an interrupt source. The 1st cell contains the interrupt
39 number. The 2nd cell is the trigger type and level flags
42 1 = low-to-high edge triggered
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| /Documentation/devicetree/bindings/sound/ |
| D | wm8994.txt | 8 - compatible : One of "wlf,wm1811", "wlf,wm8994" or "wlf,wm8958".
10 - reg : the I2C address of the device for I2C, the chip select
13 - gpio-controller : Indicates this device is a GPIO controller.
14 - #gpio-cells : Must be 2. The first cell is the pin number and the
15 second cell is used to specify optional parameters (currently unused).
17 - power supplies for the device, as covered in
20 - for wlf,wm1811 and wlf,wm8958:
21 AVDD1-supply, AVDD2-supply, DBVDD1-supply, DBVDD2-supply, DBVDD3-supply,
22 DCVDD-supply, CPVDD-supply, SPKVDD1-supply, SPKVDD2-supply
23 - for wlf,wm8994:
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| /Documentation/devicetree/bindings/iio/temperature/ |
| D | temperature-bindings.txt | 3 "include/dt-bindings/iio/temperature/thermocouple.h".
6 thermocouple-type: A single cell representing the type of the thermocouple
|
| /Documentation/devicetree/bindings/dma/ |
| D | moxa,moxart-dma.txt | 7 - compatible : Must be "moxa,moxart-dma"
8 - reg : Should contain registers location and length
9 - interrupts : Should contain an interrupt-specifier for the sole
11 - #dma-cells : Should be 1, a single cell holding a line request number
16 compatible = "moxa,moxart-dma";
19 #dma-cells = <1>;
26 described in the dma.txt file, using a two-cell specifier for each channel:
38 compatible = "moxa,moxart-mmc";
44 dma-names = "tx", "rx";
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| /Documentation/devicetree/bindings/mips/cavium/ |
| D | bootbus.txt | 7 - compatible: "cavium,octeon-3860-bootbus"
11 - reg: The base address of the Boot Bus' register bank.
13 - #address-cells: Must be <2>. The first cell is the chip select
14 within the bootbus. The second cell is the offset from the chip select.
16 - #size-cells: Must be <1>.
18 - ranges: There must be one one triplet of (child-bus-address,
19 parent-bus-address, length) for each active chip select. If the
27 - compatible: "cavium,octeon-3860-bootbus-config"
29 - cavium,cs-index: A single cell indicating the chip select that
32 - cavium,t-adr: A cell specifying the ADR timing (in nS).
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