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/Documentation/devicetree/bindings/mailbox/
Domap-mailbox.txt1 OMAP2+ and K3 Mailbox
4 The OMAP mailbox hardware facilitates communication between different processors
5 using a queued mailbox interrupt mechanism. The IP block is external to the
10 Each mailbox IP block/cluster has a certain number of h/w fifo queues and output
25 routed to different processor sub-systems on DRA7xx as they are routed through
32 Mailbox Device Node:
34 A Mailbox device node is used to represent a Mailbox IP instance/cluster within
35 a SoC. The sub-mailboxes are represented as child nodes of this parent node.
38 --------------------
39 - compatible: Should be one of the following,
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Dmtk-gce.txt8 CMDQ driver uses mailbox framework for communication. Please refer to
9 mailbox.txt for generic information about mailbox device-tree bindings.
12 - compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce" or
13 "mediatek,mt6779-gce".
14 - reg: Address range of the GCE unit
15 - interrupts: The interrupt signal from the GCE block
16 - clock: Clocks according to the common clock binding
17 - clock-names: Must be "gce" to stand for GCE clock
18 - #mbox-cells: Should be 2.
21 channel: Channel of mailbox. Be equal to the thread id of GCE.
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/Documentation/devicetree/bindings/remoteproc/
Dti,omap-remoteproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
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Dti,k3-dsp-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems
14 that are used to offload some of the processor-intensive tasks or algorithms,
17 These processor sub-systems usually contain additional sub-modules like
23 Each DSP Core sub-system is represented as a single DT node. Each node has a
29 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
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Dti,k3-r5f-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
20 Each Dual-Core R5F sub-system is represented as a single DTS node
33 - ti,am654-r5fss
34 - ti,j721e-r5fss
36 power-domains:
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/Documentation/devicetree/bindings/arm/
Darm,scmi.txt2 ----------------------------------------------------------
17 - compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports
18 - mboxes: List of phandle and mailbox channel specifiers. It should contain
22 - shmem : List of phandle pointing to the shared memory(SHM) area as per
23 generic mailbox client binding.
24 - #address-cells : should be '1' if the device has sub-nodes, maps to
25 protocol identifier for a given sub-node.
26 - #size-cells : should be '0' as 'reg' property doesn't have any size
28 - arm,smc-id : SMC id required when using smc or hvc transports
32 - mbox-names: shall be "tx" or "rx" depending on mboxes entries.
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Darm,scpi.txt2 ----------------------------------------------------------
10 - compatible : should be
12 * "arm,scpi-pre-1.0" : For implementations complying to all
14 - mboxes: List of phandle and mailbox channel specifiers
17 - shmem : List of phandle pointing to the shared memory(SHM) area between the
18 processors using these mailboxes for IPC, one for each mailbox
22 See Documentation/devicetree/bindings/mailbox/mailbox.txt
23 for more details about the generic mailbox controller and
27 ------------------------------------------------------------
34 - compatible : should be "arm,scpi-clocks"
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/Documentation/devicetree/bindings/power/reset/
Dxlnx,zynqmp-power.txt1 --------------------------------------------------------------------
3 --------------------------------------------------------------------
4 The zynqmp-power node describes the power management configurations.
8 - compatible: Must contain: "xlnx,zynqmp-power"
9 - interrupts: Interrupt specifier
12 - mbox-names : Name given to channels seen in the 'mboxes' property.
13 "tx" - Mailbox corresponding to transmit path
14 "rx" - Mailbox corresponding to receive path
15 - mboxes : Standard property to specify a Mailbox. Each value of
17 mailbox controller device node and an args specifier
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/Documentation/devicetree/bindings/arm/keystone/
Dti,sci.txt1 Texas Instruments System Control Interface (TI-SCI) Message Protocol
2 --------------------------------------------------------------------
16 TI-SCI controller Device Node:
19 The TI-SCI node describes the Texas Instrument's System Controller entity node.
23 relationship between the TI-SCI parent node to the child node.
26 -------------------
27 - compatible: should be "ti,k2g-sci" for TI 66AK2G SoC
28 should be "ti,am654-sci" for for TI AM654 SoC
29 - mbox-names:
30 "rx" - Mailbox corresponding to receive path
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/Documentation/devicetree/bindings/usb/
Domap-usb.txt4 - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb"
5 - ti,hwmods : must be "usb_otg_hs"
6 - multipoint : Should be "1" indicating the musb controller supports
7 multipoint. This is a MUSB configuration-specific setting.
8 - num-eps : Specifies the number of endpoints. This is also a
9 MUSB configuration-specific setting. Should be set to "16"
10 - ram-bits : Specifies the ram address size. Should be set to "12"
11 - interface-type : This is a board specific setting to describe the type of
14 - mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
16 - power : Should be "50". This signifies the controller can supply up to
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/Documentation/devicetree/bindings/arm/freescale/
Dfsl,scu.txt2 --------------------------------------------------------------------
4 The System Controller Firmware (SCFW) is a low-level system function
5 which runs on a dedicated Cortex-M core to provide power, clock, and
9 The AP communicates with the SC using a multi-ported MU module found
22 -------------------
23 - compatible: should be "fsl,imx-scu".
24 - mbox-names: should include "tx0", "tx1", "tx2", "tx3",
27 - mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for
50 See Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
51 for detailed mailbox binding.
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/Documentation/process/
D2.Process.rst14 ---------------
16 The kernel developers use a loosely time-based release process, with a new
53 be called 5.6-rc1. The -rc1 release is the signal that the time to
63 exception is made for drivers for previously-unsupported hardware; if they
64 touch no in-tree code, they cannot cause regressions and should be safe to
68 time. Linus releases new -rc kernels about once a week; a normal series
69 will get up to somewhere between -rc6 and -rc9 before the kernel is
78 September 30 5.4-rc1, merge window closes
79 October 6 5.4-rc2
80 October 13 5.4-rc3
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