Home
last modified time | relevance | path

Searched +full:sub +full:- +full:system (Results 1 – 25 of 194) sorted by relevance

12345678

/Documentation/devicetree/bindings/remoteproc/
Dti,omap-remoteproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
15 other hardware accelerators, for achieving various system level goals.
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
[all …]
Dti,davinci-rproc.txt4 Binding status: Unstable - Subject to changes for DT representation of clocks
7 The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that
8 is used to offload some of the processor-intensive tasks or algorithms, for
9 achieving various system level goals.
11 The processor cores in the sub-system usually contain additional sub-modules
18 Each DSP Core sub-system is represented as a single DT node.
21 --------------------
24 - compatible: Should be one of the following,
25 "ti,da850-dsp" for DSPs on OMAP-L138 SoCs
27 - reg: Should contain an entry for each value in 'reg-names'.
[all …]
Dqcom,q6v5.txt6 - compatible:
10 "qcom,q6v5-pil",
11 "qcom,ipq8074-wcss-pil"
12 "qcom,msm8916-mss-pil",
13 "qcom,msm8974-mss-pil"
14 "qcom,msm8996-mss-pil"
15 "qcom,msm8998-mss-pil"
16 "qcom,sc7180-mss-pil"
17 "qcom,sdm845-mss-pil"
19 - reg:
[all …]
Dti,k3-dsp-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems
14 that are used to offload some of the processor-intensive tasks or algorithms,
15 for achieving various system level goals.
17 These processor sub-systems usually contain additional sub-modules like
23 Each DSP Core sub-system is represented as a single DT node. Each node has a
[all …]
/Documentation/devicetree/bindings/mailbox/
Dmtk-gce.txt9 mailbox.txt for generic information about mailbox device-tree bindings.
12 - compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce" or
13 "mediatek,mt6779-gce".
14 - reg: Address range of the GCE unit
15 - interrupts: The interrupt signal from the GCE block
16 - clock: Clocks according to the common clock binding
17 - clock-names: Must be "gce" to stand for GCE clock
18 - #mbox-cells: Should be 2.
25 - mboxes: Client use mailbox to communicate with GCE, it should have this
28 - mediatek,gce-client-reg: Specify the sub-system id which is corresponding
[all …]
/Documentation/devicetree/bindings/regulator/
Dmax8907.txt4 - compatible: "maxim,max8907"
5 - reg: I2C slave address
6 - interrupts: The interrupt output of the controller
7 - mbatt-supply: The input supply for MBATT, BBAT, SDBY, VRTC.
8 - in-v1-supply: The input supply for SD1.
9 - in-v2-supply: The input supply for SD2.
10 - in-v3-supply: The input supply for SD3.
11 - in1-supply: The input supply for LDO1.
13 - in20-supply: The input supply for LDO20.
14 - regulators: A node that houses a sub-node for each regulator within the
[all …]
Dpalmas-pmic.txt11 - compatible : Should be from the list
12 ti,twl6035-pmic
13 ti,twl6036-pmic
14 ti,twl6037-pmic
15 ti,tps65913-pmic
16 ti,tps65914-pmic
17 ti,tps65917-pmic
18 ti,tps659038-pmic
20 ti,palmas-pmic
21 - interrupts : The interrupt number and the type which can be looked up here:
[all …]
Dtps65132-regulator.txt4 - compatible: "ti,tps65132"
5 - reg: I2C slave address
8 Device supports two regulators OUTP and OUTN. A sub node within the
9 device node describe the properties of these regulators. The sub-node
11 -For regulator outp, the sub node name should be "outp".
12 -For regulator outn, the sub node name should be "outn".
14 -enable-gpios:(active high, output) Regulators are controlled by the input pins.
15 If it is connected to GPIO through host system then provide the
17 -active-discharge-gpios: (active high, output) Some configurations use delay mechanisms
20 the delay mechanism. Requires specification of ti,active-discharge-time-us
[all …]
Dtps6586x.txt4 - compatible: "ti,tps6586x"
5 - reg: I2C slave address
6 - interrupts: the interrupt outputs of the controller
7 - #gpio-cells: number of cells to describe a GPIO
8 - gpio-controller: mark the device as a GPIO controller
9 - regulators: A node that houses a sub-node for each regulator within the
10 device. Each sub-node is identified using the node's name (or the deprecated
11 regulator-compatible property if present), with valid values listed below.
12 The content of each sub-node is defined by the standard binding for
14 sys, sm[0-2], ldo[0-9] and ldo_rtc
[all …]
/Documentation/devicetree/bindings/mfd/
Dmax77620.txt4 -------------------
5 - compatible: Must be one of
9 - reg: I2C device address.
12 -------------------
13 - interrupts: The interrupt on the parent the controller is
15 - interrupt-controller: Marks the device node as an interrupt controller.
16 - #interrupt-cells: is <2> and their usage is compliant to the 2 cells
17 variant of <../interrupt-controller/interrupts.txt>
19 are defined at dt-bindings/mfd/max77620.h.
21 - system-power-controller: Indicates that this PMIC is controlling the
[all …]
Dsamsung,sec-core.txt1 Binding for Samsung S2M and S5M family multi-function device
4 This is a part of device tree bindings for S2M and S5M family multi-function
8 of multi-function devices which include voltage and current regulators, RTC,
9 charger controller, clock outputs and other sub-blocks. It is interfaced
10 to the host controller using an I2C interface. Each sub-block is usually
11 addressed by the host system using different I2C slave addresses.
14 This document describes bindings for main device node. Optional sub-blocks
15 must be a sub-nodes to it. Bindings for them can be found in:
16 - bindings/regulator/samsung,s2mpa01.txt
17 - bindings/regulator/samsung,s2mps11.txt
[all …]
/Documentation/userspace-api/media/
Dglossary.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
33 A character device node in the file system used to control and
51 **Field-programmable Gate Array**
56 See https://en.wikipedia.org/wiki/Field-programmable_gate_array.
65 together make a larger user-facing functional peripheral. For
73 **Inter-Integrated Circuit**
75 A multi-master, multi-slave, packet switched, single-ended,
77 like sub-device hardware components.
79 See http://www.nxp.com/docs/en/user-guide/UM10204.pdf.
113 - :term:`CEC API`;
[all …]
/Documentation/devicetree/bindings/pinctrl/
Dberlin,pinctrl.txt1 * Pin-controller driver for the Marvell Berlin SoCs
3 Pin control registers are part of both chip controller and system
4 controller register sets. Pin controller nodes should be a sub-node of
5 either the chip controller or system controller node. The pins
9 A pin-controller node should contain subnodes representing the pin group
14 is called a 'function' in the pin-controller subsystem.
17 - compatible: should be one of:
18 "marvell,berlin2-soc-pinctrl",
19 "marvell,berlin2-system-pinctrl",
20 "marvell,berlin2cd-soc-pinctrl",
[all …]
Dimg,pistachio-pinctrl.txt5 interrupt controller, and pinmux + pinconf device. The system ("east") pin
8 each. The GPIO banks are represented as sub-nodes of the pad controller node.
10 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
11 ../interrupt-controller/interrupts.txt for generic information regarding
15 --------------------------------------------
16 - compatible: "img,pistachio-system-pinctrl".
17 - reg: Address range of the pinctrl registers.
19 Required properties for GPIO bank sub-nodes:
20 --------------------------------------------
21 - interrupts: Interrupt line for the GPIO bank.
[all …]
/Documentation/arm/keystone/
Dknav-qmss.rst9 The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of
10 the main hardware sub system which forms the backbone of the Keystone
11 multi-core Navigator. QMSS consist of queue managers, packed-data structure
15 management of the packet queues. Packets are queued/de-queued by writing or
29 Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt
40 git://git.ti.com/keystone-rtos/qmss-lld.git
43 channels. This firmware is available under ti-keystone folder of
46 git://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git
49 ubifs file system and provide a sym link to k2_qmss_pdsp_acc48_k2_le_1_0_0_9.bin
50 in the file system and boot up the kernel. User would see
[all …]
/Documentation/leds/
Dleds-class-flash.rst5 Some LED devices provide two modes - torch and flash. In the LED subsystem
6 those modes are supported by LED class (see Documentation/leds/leds-class.rst)
16 (see Documentation/ABI/testing/sysfs-class-led-flash)
18 - flash_brightness
19 - max_flash_brightness
20 - flash_timeout
21 - max_flash_timeout
22 - flash_strobe
23 - flash_fault
36 - dev:
[all …]
/Documentation/ABI/testing/
Dsysfs-bus-nvdimm7 The libnvdimm sub-system implements a common sysfs interface for
8 platform nvdimm resources. See Documentation/driver-api/nvdimm/.
Dsysfs-bus-nfit8 Contact: linux-nvdimm@lists.01.org
10 (RO) Serial number of the NVDIMM (non-volatile dual in-line
17 Contact: linux-nvdimm@lists.01.org
26 Contact: linux-nvdimm@lists.01.org
34 Contact: linux-nvdimm@lists.01.org
42 Contact: linux-nvdimm@lists.01.org
44 (RO) Handle (i.e., instance number) for the SMBIOS (system
52 Contact: linux-nvdimm@lists.01.org
54 (RO) The flags in the NFIT memory device sub-structure indicate
71 Contact: linux-nvdimm@lists.01.org
[all …]
/Documentation/devicetree/bindings/mtd/
Dcortina,gemini-flash.txt4 some special bits that can be controlled by the machine's system controller.
7 - compatible : must be "cortina,gemini-flash", "cfi-flash";
8 - reg : memory address for the flash chip
9 - syscon : must be a phandle to the system controller
10 - bank-width : width in bytes of flash interface, should be <2>
12 For the rest of the properties, see mtd-physmap.txt.
14 The device tree may optionally contain sub-nodes describing partitions of the
20 compatible = "cortina,gemini-flash", "cfi-flash";
23 bank-width = <2>;
/Documentation/devicetree/bindings/arm/
Djuno,scpi.txt1 System Control and Power Interface (SCPI) Message Protocol
5 ------------------------------------
8 - compatible : should be "arm,juno-sram-ns" for Non-secure SRAM
10 Each sub-node represents the reserved area for SCPI.
12 Required sub-node properties:
13 - reg : The base offset and size of the reserved area with the SRAM
14 - compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based
18 --------------------------------------------------------------
20 - compatible : should be "arm,scpi-sensors".
21 - #thermal-sensor-cells: should be set to 1.
Dsyna.txt3 According to https://www.synaptics.com/company/news/conexant-marvell
7 ---------------------------------------------------------------
19 ---------------------------------------------------------------
34 "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
36 "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
42 model = "Sony NSZ-GS7";
43 compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
54 - compatible: should be "marvell,berlin-cpu-ctrl"
55 - reg: address and length of the register set
59 cpu-ctrl@f7dd0000 {
[all …]
Damlogic,scpi.txt1 System Control and Power Interface (SCPI) Message Protocol
3 ----------------------------------------------------------
6 - compatible : should be "amlogic,meson-gxbb-scpi"
9 ------------------------------------
12 - compatible : should be "amlogic,meson-gxbb-sram"
14 Each sub-node represents the reserved area for SCPI.
16 Required sub-node properties:
17 - compatible : should be "amlogic,meson-gxbb-scp-shmem" for SRAM based shared
21 --------------------------------------------------------------
25 - compatible : should be "amlogic,meson-gxbb-scpi-sensors".
/Documentation/driver-api/media/
Dv4l2-subdev.rst1 .. SPDX-License-Identifier: GPL-2.0
3 V4L2 sub-devices
4 ----------------
6 Many drivers need to communicate with sub-devices. These devices can do all
8 encoding or decoding. For webcams common sub-devices are sensors and camera
12 driver with a consistent interface to these sub-devices the
13 :c:type:`v4l2_subdev` struct (v4l2-subdev.h) was created.
15 Each sub-device driver must have a :c:type:`v4l2_subdev` struct. This struct
16 can be stand-alone for simple sub-devices or it might be embedded in a larger
18 low-level device struct (e.g. ``i2c_client``) that contains the device data as
[all …]
/Documentation/userspace-api/media/v4l/
Dopen.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
22 the hardware, which may also expose device nodes, called V4L2 sub-devices.
24 When such V4L2 sub-devices are exposed, they allow controlling those
25 other hardware components - usually connected via a serial bus (like
26 I²C, SMBus or SPI). Depending on the bridge driver, those sub-devices
29 :ref:`V4L2 sub-devices <subdev>`.
32 :ref:`Media Controller <media_controller>` are called **MC-centric**
34 are called **video-node-centric**.
36 Userspace can check if a V4L2 hardware peripheral is MC-centric by
38 :ref:`device_caps field <device-capabilities>`.
[all …]
/Documentation/devicetree/bindings/arm/freescale/
Dfsl,vf610-mscm-cpucfg.txt1 Freescale Vybrid Miscellaneous System Control - CPU Configuration
3 The MSCM IP contains multiple sub modules, this binding describes the first
7 - compatible: "fsl,vf610-mscm-cpucfg", "syscon"
8 - reg: the register range of the MSCM CPU configuration registers
12 compatible = "fsl,vf610-mscm-cpucfg", "syscon";

12345678