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/Documentation/devicetree/bindings/media/xilinx/
Dxlnx,v-tc.txt1 Xilinx Video Timing Controller (VTC)
4 The Video Timing Controller is a general purpose video timing generator and
13 - clocks: Must contain a clock specifier for the VTC core and timing
18 - xlnx,detector: The VTC has a timing detector
19 - xlnx,generator: The VTC has a timing generator
Dxlnx,v-tpg.txt26 - xlnx,vtc: A phandle referencing the Video Timing Controller that generates
29 - timing-gpios: Specifier for a GPIO that controls the timing mux at the TPG
33 The xlnx,vtc and timing-gpios properties are mandatory when the TPG is
44 timing-gpios = <&ps7_gpio_0 55 GPIO_ACTIVE_LOW>;
/Documentation/driver-api/memory-devices/
Dti-gpmc.rst20 GPMC generic timing calculation:
29 generic timing routine was developed to achieve above requirements.
37 happen that timing as specified by peripheral datasheet is not present
38 in timing structure, in this scenario, try to correlate peripheral
39 timing to the one available. If that doesn't work, try to add a new
40 field as required by peripheral, educate generic timing routine to
45 Generic timing routine has been verified to work properly on
48 A word of caution: generic timing routine has been developed based
50 custom timing routines, a kind of reverse engineering without
52 in mainline having custom timing routine) and by simulation.
[all …]
/Documentation/devicetree/bindings/mmc/
Dsdhci-am654.yaml52 description: Output tap delay for SD/MMC legacy timing
58 description: Output tap delay for MMC high speed timing
64 description: Output tap delay for SD high speed timing
70 description: Output tap delay for SD UHS SDR12 timing
76 description: Output tap delay for SD UHS SDR25 timing
82 description: Output tap delay for SD UHS SDR50 timing
88 description: Output tap delay for SD UHS SDR104 timing
94 description: Output tap delay for SD UHS DDR50 timing
100 description: Output tap delay for eMMC DDR52 timing
106 description: Output tap delay for eMMC HS200 timing
[all …]
Dsdhci-sprd.txt33 - sprd,phy-delay-legacy: Delay value for legacy timing.
34 - sprd,phy-delay-sd-highspeed: Delay value for SD high-speed timing.
35 - sprd,phy-delay-sd-uhs-sdr50: Delay value for SD UHS SDR50 timing.
36 - sprd,phy-delay-sd-uhs-sdr104: Delay value for SD UHS SDR50 timing.
37 - sprd,phy-delay-mmc-highspeed: Delay value for MMC high-speed timing.
38 - sprd,phy-delay-mmc-ddr52: Delay value for MMC DDR52 timing.
39 - sprd,phy-delay-mmc-hs200: Delay value for MMC HS200 timing.
40 - sprd,phy-delay-mmc-hs400: Delay value for MMC HS400 timing.
41 - sprd,phy-delay-mmc-hs400es: Delay value for MMC HS400 enhanced strobe timing.
Dexynos-dw-mshc.txt30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
35 * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
39 * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
42 Notes for the sdr-timing and ddr-timing values:
48 Valid values for SDR and DDR CIU clock timing for Exynos5250:
87 samsung,dw-mshc-sdr-timing = <2 3>;
88 samsung,dw-mshc-ddr-timing = <1 2>;
89 samsung,dw-mshc-hs400-timing = <0 2>;
Dcdns,sdhci.yaml38 description: Value of the delay in the input path for SD high-speed timing
44 description: Value of the delay in the input path for legacy timing
50 description: Value of the delay in the input path for SD UHS SDR12 timing
56 description: Value of the delay in the input path for SD UHS SDR25 timing
62 description: Value of the delay in the input path for SD UHS SDR50 timing
68 description: Value of the delay in the input path for SD UHS DDR50 timing
74 description: Value of the delay in the input path for MMC high-speed timing
80 description: Value of the delay in the input path for eMMC high-speed DDR timing
/Documentation/devicetree/bindings/ata/
Dahci-ceva.txt8 - ceva,p0-cominit-params: OOB timing value for COMINIT parameter for port 0.
9 - ceva,p1-cominit-params: OOB timing value for COMINIT parameter for port 1.
16 - ceva,p0-comwake-params: OOB timing value for COMWAKE parameter for port 0.
17 - ceva,p1-comwake-params: OOB timing value for COMWAKE parameter for port 1.
24 - ceva,p0-burst-params: Burst timing value for COM parameter for port 0.
25 - ceva,p1-burst-params: Burst timing value for COM parameter for port 1.
32 - ceva,p0-retry-params: Retry interval timing value for port 0.
33 - ceva,p1-retry-params: Retry interval timing value for port 1.
/Documentation/devicetree/bindings/mips/cavium/
Dbootbus.txt32 - cavium,t-adr: A cell specifying the ADR timing (in nS).
34 - cavium,t-ce: A cell specifying the CE timing (in nS).
36 - cavium,t-oe: A cell specifying the OE timing (in nS).
38 - cavium,t-we: A cell specifying the WE timing (in nS).
40 - cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS).
42 - cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS).
44 - cavium,t-pause: A cell specifying the PAUSE timing (in nS).
46 - cavium,t-wait: A cell specifying the WAIT timing (in nS).
48 - cavium,t-page: A cell specifying the PAGE timing (in nS).
50 - cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS).
/Documentation/devicetree/bindings/clock/
Dnvidia,tegra124-car.txt29 - nvidia,ram-code : Should contain the value of RAM_CODE this timing set
32 Each "emc-timings" node should contain a "timing" subnode for every supported
35 Required properties for "timing" nodes :
36 - clock-frequency : Should contain the memory clock rate to which this timing
39 parent of the EMC clock should be running at this timing.
44 timing.
93 timing-12750000 {
99 timing-20400000 {
/Documentation/devicetree/bindings/display/panel/
Ddisplay-timings.yaml18 and to specify the timing that is native for the display.
27 The default display timing is the one specified as native-mode.
32 "^timing":
35 - $ref: panel-timing.yaml#
43 * Example that specifies panel timing using minimum, typical,
Dpanel-timing.yaml4 $id: http://devicetree.org/schemas/display/panel/panel-timing.yaml#
7 title: panel timing bindings
14 There are different ways of describing the timing data of a panel. The
46 This matches the timing diagrams often found in data sheets.
56 Timing can be specified either as a typical value or as a tuple
73 description: Horizontal front porch panel timing
86 description: Horizontal back porch timing
99 description: Horizontal sync length panel timing
112 description: Vertical front porch panel timing
125 description: Vertical back porch panel timing
[all …]
Dpanel-dpi.yaml28 panel-timing: true
35 - panel-timing
53 panel-timing {
Dsgd,gktw70sdae4se.yaml31 panel-timing: true
49 panel-timing {
Dadvantech,idk-2121wr.yaml37 panel-timing: true
75 - panel-timing
88 panel-timing {
Dmitsubishi,aa121td01.yaml34 panel-timing: true
54 panel-timing {
Dadvantech,idk-1110wr.yaml31 panel-timing: true
49 panel-timing {
Dmitsubishi,aa104xd12.yaml34 panel-timing: true
55 panel-timing {
/Documentation/devicetree/bindings/bus/
Dimx-weim.txt51 Timing property for child nodes. It is mandatory, not optional.
53 - fsl,weim-cs-timing: The timing array, contains timing values for the
83 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
90 In this case, both chip select 0 and 1 will be configured with the same timing
109 fsl,weim-cs-timing = <0x024400b1 0x00001010 0x20081100
/Documentation/devicetree/bindings/display/exynos/
Dexynos7-decon.txt30 - i80-if-timings: timing configuration for lcd i80 interface support.
34 - display-timings: timing settings for DECON, as described in document [1].
38 [1]: Documentation/devicetree/bindings/display/panel/display-timing.txt
/Documentation/userspace-api/media/v4l/
Dvidioc-g-dv-timings.rst48 applications use the :ref:`VIDIOC_G_DV_TIMINGS <VIDIOC_G_DV_TIMINGS>` ioctl. The detailed timing
52 structure as argument. If the ioctl is not supported or the timing
185 - Type of DV timings as listed in :ref:`dv-timing-types`.
199 .. _dv-timing-types:
201 .. flat-table:: DV Timing types
206 * - Timing type
220 .. flat-table:: DV BT Timing standards
224 * - Timing standard
243 .. flat-table:: DV BT Timing flags
/Documentation/devicetree/bindings/media/i2c/
Ddongwoon,dw9768.yaml49 dongwoon,aac-timing:
51 Number of AAC Timing count that controlled by one 6-bit period of
93 dongwoon,aac-timing = <0x39>;
/Documentation/devicetree/bindings/ddr/
Dlpddr3-timings.txt1 * AC timing parameters of LPDDR3 memories for a given speed-bin.
12 The following properties represent AC timing parameters from the memory
Dlpddr2-timings.txt1 * AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin
10 The following properties represent AC timing parameters from the memory
/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra124-mc.yaml50 Value of RAM_CODE this timing set is used for.
53 "^timing-[0-9]+$":
126 timing-12750000 {

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