| /Documentation/userspace-api/media/cec/ |
| D | cec-pin-error-inj.rst | 35 # clear clear all rx and tx error injections
37 # tx-clear clear all tx error injections
38 # <op> clear clear all rx and tx error injections for <op>
40 # <op> tx-clear clear all tx error injections for <op>
49 # TX error injection settings:
50 # tx-ignore-nack-until-eom ignore early NACKs until EOM
51 # tx-custom-low-usecs <usecs> define the 'low' time for the custom pulse
52 # tx-custom-high-usecs <usecs> define the 'high' time for the custom pulse
53 # tx-custom-pulse transmit the custom pulse once the bus is idle
55 # TX error injection:
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| /Documentation/devicetree/bindings/display/msm/ |
| D | hdmi.txt | 5 * "qcom,hdmi-tx-8996"
6 * "qcom,hdmi-tx-8994"
7 * "qcom,hdmi-tx-8084"
8 * "qcom,hdmi-tx-8974"
9 * "qcom,hdmi-tx-8660"
10 * "qcom,hdmi-tx-8960"
24 - qcom,hdmi-tx-mux-en-gpios: hdmi mux enable pin
25 - qcom,hdmi-tx-mux-sel-gpios: hdmi mux select pin
26 - qcom,hdmi-tx-mux-lpm-gpios: hdmi mux lpm pin
61 compatible = "qcom,hdmi-tx-8960";
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | renesas,dw-hdmi.txt | 1 Renesas Gen3 DWC HDMI TX Encoder
4 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
15 - "renesas,r8a774a1-hdmi" for R8A774A1 (RZ/G2M) compatible HDMI TX
16 - "renesas,r8a774b1-hdmi" for R8A774B1 (RZ/G2N) compatible HDMI TX
17 - "renesas,r8a774e1-hdmi" for R8A774E1 (RZ/G2H) compatible HDMI TX
18 - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
19 - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
20 - "renesas,r8a77961-hdmi" for R8A77961 (R-Car M3-W+) compatible HDMI TX
21 - "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX
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| D | dw_hdmi.txt | 1 Synopsys DesignWare HDMI TX Encoder
5 TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding
13 - reg: Memory mapped base address and length of the DWC HDMI TX registers.
19 - interrupts: Reference to the DWC HDMI TX interrupt.
24 - clock-names: The DWC HDMI TX uses the following clocks.
30 - ports: The connectivity of the DWC HDMI TX with the rest of the system is
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| /Documentation/devicetree/bindings/net/ |
| D | micrel-ksz90x1.txt | 51 - txen-skew-ps : Skew control of TX CTL pad
56 - txd0-skew-ps : Skew control of TX data 0 pad
57 - txd1-skew-ps : Skew control of TX data 1 pad
58 - txd2-skew-ps : Skew control of TX data 2 pad
59 - txd3-skew-ps : Skew control of TX data 3 pad
73 - txc-skew-ps : Skew control of TX clock pad
78 - txen-skew-ps : Skew control of TX CTL pad
83 - txd0-skew-ps : Skew control of TX data 0 pad
84 - txd1-skew-ps : Skew control of TX data 1 pad
85 - txd2-skew-ps : Skew control of TX data 2 pad
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| D | sff,sfp.txt | 22 - tx-fault-gpios : GPIO phandle and a specifier of the Module Transmitter
25 - tx-disable-gpios : GPIO phandle and a specifier of the Transmitter Disable
26 output gpio signal, active (Tx disable) high
32 - rate-select1-gpios : GPIO phandle and a specifier of the Tx Signaling Rate
33 Select (AKA RS1) output gpio signal (SFP+ only), low: low Tx rate, high:
34 high Tx rate. Must not be present for SFF modules
50 tx-disable-gpios = <&cps_gpio1 24 GPIO_ACTIVE_HIGH>;
51 tx-fault-gpios = <&cpm_gpio2 19 GPIO_ACTIVE_HIGH>;
69 tx-disable-gpios = <&cps_gpio1 29 GPIO_ACTIVE_HIGH>;
70 tx-fault-gpios = <&cps_gpio1 26 GPIO_ACTIVE_HIGH>;
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| D | snps,dwmac.yaml | 166 snps,mtl-tx-config:
169 Multiple TX Queues parameters. Phandle to a node that can
171 * snps,tx-queues-to-use, number of TX queues to be used in the
173 * Choose one of these TX scheduling algorithms
174 * snps,tx-sched-wrr, Weighted Round Robin
175 * snps,tx-sched-wfq, Weighted Fair Queuing
176 * snps,tx-sched-dwrr, Deficit Weighted Round Robin
177 * snps,tx-sched-sp, Strict priority
178 * For each TX queue
179 * snps,weight, TX queue weight (if using a DCB weight
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| D | xilinx_axienet.txt | 7 segments of memory for buffering TX and RX, as well as the capability of
8 offloading TX/RX checksum calculation off the processor.
24 - interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
26 specified, the TX/RX DMA interrupts should be on that node
31 - xlnx,rxmem : Set to allocated memory buffer for Rx/Tx in the hardware
37 - xlnx,txcsum : 0 or empty for disabling TX checksum offload,
38 1 to enable partial TX checksum offload,
39 2 to enable full TX checksum offload
49 device (DMA registers and DMA TX/RX interrupts) rather
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| D | lantiq,xrx200-net.txt | 9 - interrupts : TX and RX DMA interrupts. Use interrupt-names "tx" for
10 : the TX interrupt and "rx" for the RX interrupt.
20 interrupt-names = "tx", "rx";
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| /Documentation/devicetree/bindings/dma/ |
| D | fsl-mxs-dma.txt | 41 interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
43 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
44 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
59 dma-names = "rx", "tx";
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| /Documentation/devicetree/bindings/mfd/ |
| D | atmel-usart.txt | 27 The order of DMA channels is fixed. The first DMA channel must be TX
30 - dma-names: "tx" for TX channel.
32 The order of dma-names is also fixed. The first name must be "tx"
37 - atmel,use-dma-tx: use of PDC or DMA for transmitting data
41 - atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO
43 - rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: see rs485.txt
58 atmel,use-dma-tx;
75 atmel,use-dma-tx;
78 dma-names = "tx", "rx";
96 dma-names = "tx", "rx";
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,wcnss.txt | 57 Definition: should specify the "rx" and "tx" interrupts
62 Definition: must contain "rx" and "tx"
67 Definition: should reference the tx-enable and tx-rings-empty SMEM states
72 Definition: must contain "tx-enable" and "tx-rings-empty"
108 interrupt-names = "tx", "rx";
111 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
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| /Documentation/devicetree/bindings/serial/ |
| D | mrvl,pxa-ssp.txt | 15 - dmas: Two dma phandles, one for rx, one for tx
16 - dma-names: Must be "rx", "tx"
29 dma-names = "rx", "tx";
40 dma-names = "rx", "tx";
51 dma-names = "rx", "tx";
62 dma-names = "rx", "tx";
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| D | mvebu-uart.txt | 20 (marvell,armada-3700-uart): "uart-sum", "uart-tx" and "uart-rx",
21 respectively the UART sum interrupt, the UART TX interrupt and
25 (marvell,armada-3700-uart-ext): "uart-tx" and "uart-rx",
26 respectively the UART TX interrupt and the UART RX interrupt. A
42 interrupt-names = "uart-sum", "uart-tx", "uart-rx";
52 interrupt-names = "uart-tx", "uart-rx";
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| /Documentation/ABI/testing/ |
| D | sysfs-class-net-queues | 19 What: /sys/class/net/<iface>/queues/tx-<queue>/tx_timeout
27 What: /sys/class/net/<iface>/queues/tx-<queue>/tx_maxrate
35 What: /sys/class/net/<iface>/queues/tx-<queue>/xps_cpus
45 What: /sys/class/net/<iface>/queues/tx-<queue>/xps_rxqs
56 What: /sys/class/net/<iface>/queues/tx-<queue>/byte_queue_limits/hold_time
65 What: /sys/class/net/<iface>/queues/tx-<queue>/byte_queue_limits/inflight
73 What: /sys/class/net/<iface>/queues/tx-<queue>/byte_queue_limits/limit
82 What: /sys/class/net/<iface>/queues/tx-<queue>/byte_queue_limits/limit_max
91 What: /sys/class/net/<iface>/queues/tx-<queue>/byte_queue_limits/limit_min
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| /Documentation/devicetree/bindings/phy/ |
| D | apm-xgene-phy.txt | 17 - apm,tx-eye-tuning : Manual control to fine tune the capture of the serial
22 - apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample
27 - apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit)
31 - apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for
35 - apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of
39 - apm,tx-pre-cursor2 : 2st pre-cursor emphasis taps control. Two set of
43 - apm,tx-post-cursor : Post-cursor emphasis taps control. Two set of
46 - apm,tx-speed : Tx operating speed. One set of 3-tuple for each
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| D | mxs-usb-phy.txt | 17 - fsl,tx-cal-45-dn-ohms: Integer [30-55]. Resistance (in ohms) of switchable
20 - fsl,tx-cal-45-dp-ohms: Integer [30-55]. Resistance (in ohms) of switchable
23 - fsl,tx-d-cal: Integer [79-119]. Current trimming value (as a percentage) of
24 the 17.78mA TX reference current. Default: 100
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| /Documentation/devicetree/bindings/net/can/ |
| D | xilinx_can.txt | 19 - tx-fifo-depth : Can Tx fifo depth (Zynq, Axi CAN).
22 - tx-mailbox-count : Can Tx mailbox buffer count (CAN FD).
37 tx-fifo-depth = <0x40>;
48 tx-fifo-depth = <0x40>;
59 tx-mailbox-count = <0x20>;
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| /Documentation/devicetree/bindings/sound/ |
| D | zte,zx-spdif.txt | 7 - clock-names: "tx" for the clock to the SPDIF interface.
10 - dma-names : Must be "tx"
23 clock-names = "tx";
26 dma-names = "tx";
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| D | davinci-mcasp-audio.txt | 21 (0 - INACTIVE, 1 - TX, 2 - RX)
26 identifiers must be "rx" and "tx".
31 - tx-num-evt : FIFO levels.
33 - dismod : Specify the drive on TX pin during inactive slots
41 - interrupt-names : Known interrupt names are "tx" and "rx"
75 interrupt-names = "tx", "rx";
79 0 0 0 0 /* 0: INACTIVE, 1: TX, 2: RX */
83 tx-num-evt = <1>;
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| D | adi,axi-spdif-tx.txt | 4 - compatible : Must be "adi,axi-spdif-tx-1.00.a"
13 - dma-names : Must be "tx"
24 compatible = "adi,axi-spdif-tx-1.00.a";
29 dma-names = "tx";
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| D | tdm-slot.txt | 8 dai-tdm-slot-tx-mask : Transmit direction slot mask, optional
14 dai-tdm-slot-tx-mask = <0 1>;
20 tx and rx masks.
22 For snd_soc_of_xlate_tdm_slot_mask(), the tx and rx masks will use a 1 bit
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| /Documentation/networking/ |
| D | driver.rst | 28 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
34 ... update tx consumer index ...
45 And then at the end of your TX reclamation event handling::
73 For example, this means that it is not allowed for your TX
74 mitigation scheme to let TX packets "hang out" in the TX
75 ring unreclaimed forever if no new TX packets are sent.
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| /Documentation/devicetree/bindings/mailbox/ |
| D | omap-mailbox.txt | 17 and tx interrupt source per h/w fifo. Communication between different processors
18 is achieved through the appropriate programming of the rx and tx interrupt
83 - ti,mbox-tx: sub-mailbox descriptor property defining a Tx fifo
88 Each of the above ti,mbox-tx and ti,mbox-rx properties should have 3 cells of
91 (ti,mbox-tx) or for receiving (ti,mbox-rx)
97 associated with generating a tx/rx fifo interrupt.
102 to send messages without triggering a Tx ready interrupt,
103 and to control the Tx ticker. Should be used only on
132 ti,mbox-tx = <0 0 0>;
136 ti,mbox-tx = <3 0 0>;
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| /Documentation/networking/device_drivers/ethernet/freescale/ |
| D | dpaa.rst | 44 -Ports / Tx Rx \ ... / Tx Rx \
62 |Rx | |Rx | |Tx | |Tx | | driver |
85 Tx Cnf FQ Tx confirmation FQs
86 Tx FQs transmission frame queues
142 On Tx, all transmitted frames are returned to the driver through Tx
155 The driver has Rx and Tx checksum offloading for UDP and TCP. Currently the Rx
162 The driver has support for multiple prioritized Tx traffic classes. Priorities
164 strict priority levels. Each traffic class contains NR_CPU TX queues. By
165 default, only one traffic class is enabled and the lowest priority Tx queues
184 Traffic coming on the DPAA Rx queues or on the DPAA Tx confirmation
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