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/Documentation/userspace-api/media/v4l/
Ddev-mem2mem.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
6 Video Memory-To-Memory Interface
9 A V4L2 memory-to-memory device can compress, decompress, transform, or
10 otherwise convert video data from one format into another format, in memory.
11 Such memory-to-memory devices set the ``V4L2_CAP_VIDEO_M2M`` or
12 ``V4L2_CAP_VIDEO_M2M_MPLANE`` capability. Examples of memory-to-memory
16 A memory-to-memory video node acts just like a normal video node, but it
23 Memory-to-memory devices function as a shared resource: you can
24 open the video node multiple times, each application setting up their
28 This is different from the usual video node behavior where the video
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Dpixfmt-compressed.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
8 .. _compressed-formats:
12 .. flat-table:: Compressed Image Formats
13 :header-rows: 1
14 :stub-columns: 0
17 * - Identifier
18 - Code
19 - Details
20 * .. _V4L2-PIX-FMT-JPEG:
22 - ``V4L2_PIX_FMT_JPEG``
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Dcommon.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
10 - Opening the device
12 - Changing device properties, selecting a video and audio input, video
15 - Negotiating a data format
17 - Negotiating an input/output method
19 - The actual input/output loop
21 - Closing the device
34 app-pri
35 video
39 dv-timings
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Dpixfmt-intro.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 V4L2 drivers are not limited to these formats, however. Driver-specific
14 formats are possible. In that case the application may depend on a codec
19 format, saving much disk space, and later use a codec to convert the
20 images to the X Windows screen format when the video is to be displayed.
23 specification would not be complete without well-defined standard
40 :ref:`four character (FourCC) codes <v4l2-fourcc>` which are also
46 and are referred to as "multi-planar formats". For example, a
47 :ref:`YUV422 <V4L2-PIX-FMT-YUV422M>` frame is normally stored in one
50 in the 2-planar version or with each component in its own buffer in the
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/Documentation/admin-guide/media/
Dplatform-cardlist.rst1 .. SPDX-License-Identifier: GPL-2.0
17 am437x-vpfe TI AM437x VPFE
18 aspeed-video Aspeed AST2400 and AST2500
19 atmel-isc ATMEL Image Sensor Controller (ISC)
20 atmel-isi ATMEL Image Sensor Interface (ISI)
24 cdns-csi2rx Cadence MIPI-CSI2 RX Controller
25 cdns-csi2tx Cadence MIPI-CSI2 TX Controller
26 coda-vpu Chips&Media Coda multi-standard codec IP
27 dm355_ccdc TI DM355 CCDC video capture
28 dm644x_ccdc TI DM6446 CCDC video capture
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Dpci-cardlist.rst1 .. SPDX-License-Identifier: GPL-2.0
9 - Vendor ID and device ID;
10 - Subsystem ID and Subsystem device ID;
12 The ``lspci -nn`` command allows identifying the vendor/device PCI IDs:
14 .. code-block:: none
15 :emphasize-lines: 3
17 $ lspci -nn
19 …00:0a.0 Multimedia controller [0480]: Philips Semiconductors SAA7131/SAA7133/SAA7135 Video Broadca…
21 …01:00.0 Multimedia video controller [0400]: Conexant Systems, Inc. CX23887/8 PCIe Broadcast Audio …
22 …02:01.0 Multimedia video controller [0400]: Internext Compression Inc iTVC15 (CX23415) Video Decod…
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/Documentation/devicetree/bindings/media/
Dallegro.txt1 Device-tree bindings for the Allegro DVT video IP codecs present in the Xilinx
5 Each actual codec engines is controlled by a microcontroller (MCU). Host
10 - compatible: value should be one of the following
11 "allegro,al5e-1.1", "allegro,al5e": encoder IP core
12 "allegro,al5d-1.1", "allegro,al5d": decoder IP core
13 - reg: base and length of the memory mapped register region and base and
15 - reg-names: must include "regs" and "sram"
16 - interrupts: shared interrupt from the MCUs to the processing system
17 - clocks: must contain an entry for each entry in clock-names
18 - clock-names: must include "core_clk", "mcu_clk", "m_axi_core_aclk",
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Dmediatek-vcodec.txt1 Mediatek Video Codec
3 Mediatek Video Codec is the video codec hw present in Mediatek SoCs which
7 - compatible : "mediatek,mt8173-vcodec-enc" for MT8173 encoder
8 "mediatek,mt8183-vcodec-enc" for MT8183 encoder.
9 "mediatek,mt8173-vcodec-dec" for MT8173 decoder.
10 - reg : Physical base address of the video codec registers and length of
12 - interrupts : interrupt number to the cpu.
13 - mediatek,larb : must contain the local arbiters in the current Socs.
14 - clocks : list of clock specifiers, corresponding to entries in
15 the clock-names property.
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Ds5p-mfc.txt1 * Samsung Multi Format Codec (MFC)
3 Multi Format Codec (MFC) is the IP present in Samsung SoCs which
6 video raw/elementary streams and has support for all popular
7 video codecs.
10 - compatible : value should be either one among the following
11 (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
12 (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
13 (c) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC
14 (d) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC
15 (e) "samsung,exynos5433-mfc" for MFC v8 present in Exynos5433 SoC
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Drockchip,vdec.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip Video Decoder (VDec) Device Tree Bindings
10 - Heiko Stuebner <heiko@sntech.de>
12 description: |-
13 The Rockchip rk3399 has a stateless Video Decoder that can decodes H.264,
18 const: rockchip,rk3399-vdec
28 - description: The Video Decoder AXI interface clock
29 - description: The Video Decoder AHB interface clock
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Dqcom,msm8916-venus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/media/qcom,msm8916-venus.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm Venus video encode and decode accelerators
11 - Stanimir Varbanov <stanimir.varbanov@linaro.org>
14 The Venus IP is a video encode and decode accelerator present
19 const: qcom,msm8916-venus
27 power-domains:
33 clock-names:
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Dallwinner,sun4i-a10-video-engine.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-video-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Video Engine Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - allwinner,sun4i-a10-video-engine
17 - allwinner,sun5i-a13-video-engine
18 - allwinner,sun7i-a20-video-engine
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Dmediatek-vpu.txt1 * Mediatek Video Processor Unit
3 Video Processor Unit is a HW video controller. It controls HW Codec including
7 - compatible: "mediatek,mt8173-vpu"
8 - reg: Must contain an entry for each entry in reg-names.
9 - reg-names: Must include the following entries:
12 - interrupts: interrupt number to the cpu.
13 - clocks : clock name from clock manager
14 - clock-names: must be main. It is the main clock of VPU
17 - memory-region: phandle to a node describing memory (see
18 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
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Dqcom,sc7180-venus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/media/qcom,sc7180-venus.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm Venus video encode and decode accelerators
11 - Stanimir Varbanov <stanimir.varbanov@linaro.org>
14 The Venus IP is a video encode and decode accelerator present
19 const: qcom,sc7180-venus
27 power-domains:
31 power-domain-names:
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Dqcom,sdm845-venus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/media/qcom,sdm845-venus.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm Venus video encode and decode accelerators
11 - Stanimir Varbanov <stanimir.varbanov@linaro.org>
14 The Venus IP is a video encode and decode accelerator present
19 const: qcom,sdm845-venus
27 power-domains:
33 clock-names:
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Dqcom,sdm845-venus-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/media/qcom,sdm845-venus-v2.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm Venus video encode and decode accelerators
11 - Stanimir Varbanov <stanimir.varbanov@linaro.org>
14 The Venus IP is a video encode and decode accelerator present
19 const: qcom,sdm845-venus-v2
27 power-domains:
31 power-domain-names:
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Dcoda.txt1 Chips&Media Coda multi-standard codec IP
4 Coda codec IPs are present in i.MX SoCs in various versions,
5 called VPU (Video Processing Unit).
8 - compatible : should be "fsl,<chip>-src" for i.MX SoCs:
9 (a) "fsl,imx27-vpu" for CodaDx6 present in i.MX27
10 (b) "fsl,imx51-vpu" for CodaHx4 present in i.MX51
11 (c) "fsl,imx53-vpu" for CODA7541 present in i.MX53
12 (d) "fsl,imx6q-vpu" for CODA960 present in i.MX6q
13 - reg: should be register base and length as documented in the
15 - interrupts : Should contain the VPU interrupt. For CODA960,
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Dnvidia,tegra-vde.txt1 NVIDIA Tegra Video Decoder Engine
4 - compatible : Must contain one of the following values:
5 - "nvidia,tegra20-vde"
6 - "nvidia,tegra30-vde"
7 - "nvidia,tegra114-vde"
8 - "nvidia,tegra124-vde"
9 - "nvidia,tegra132-vde"
10 - reg : Must contain an entry for each entry in reg-names.
11 - reg-names : Must include the following entries:
12 - sxe
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Dqcom,msm8996-venus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/media/qcom,msm8996-venus.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm Venus video encode and decode accelerators
11 - Stanimir Varbanov <stanimir.varbanov@linaro.org>
14 The Venus IP is a video encode and decode accelerator present
19 const: qcom,msm8996-venus
27 power-domains:
33 clock-names:
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Drockchip-vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/media/rockchip-vpu.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Ezequiel Garcia <ezequiel@collabora.com>
14 Hantro G1 video encode and decode accelerators present on Rockchip SoCs.
19 - rockchip,rk3288-vpu
20 - rockchip,rk3328-vpu
21 - rockchip,rk3399-vpu
30 interrupt-names:
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Dnxp,imx8mq-vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/media/nxp,imx8mq-vpu.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Philipp Zabel <p.zabel@pengutronix.de>
14 Hantro G1/G2 video decode accelerators present on i.MX8MQ SoCs.
18 const: nxp,imx8mq-vpu
23 reg-names:
25 - const: g1
26 - const: g2
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/Documentation/userspace-api/media/
Dintro.rst1 .. SPDX-License-Identifier: GPL-2.0
7 This document covers the Linux Kernel to Userspace API's used by video
8 and radio streaming devices, including video cameras, analog and digital
10 streaming capture and output devices, codec devices and remote controllers.
16 .. kernel-figure:: typical_media_device.svg
25 1. The :ref:`first part <v4l2spec>` covers radio, video capture and output,
30 called as DVB API, in fact it covers several different video standards
31 including DVB-T/T2, DVB-S/S2, DVB-C, ATSC, ISDB-T, ISDB-S, DTMB, etc. The
46 Mailing List (LMML) <http://vger.kernel.org/vger-lists.html#linux-media>`__.
/Documentation/driver-api/media/drivers/
Dzoran.rst1 .. SPDX-License-Identifier: GPL-2.0
8 website: http://mjpeg.sourceforge.net/driver-zoran/
12 --------------------------
15 ------------------------
24 * Zoran zr36060 MJPEG codec
28 Drivers to use: videodev, i2c-core, i2c-algo-bit,
31 Inputs/outputs: Composite and S-video
41 * Zoran zr36060 MJPEG codec
45 Drivers to use: videodev, i2c-core, i2c-algo-bit,
49 Six physical inputs. 1-6 are composite,
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/Documentation/sound/cards/
Dsb-live-mixer.rst19 (index 0) for a given card) allows to forward 48kHz, stereo, 16-bit
22 to 8 raw PCM devices operating at 48kHz, 16-bit little endian. It would
24 but the conversion routines exist only for stereo (2-channel streams)
34 functionality. Only the default build-in code in the ALSA driver is described
48 one-way three wire serial bus for digital sound by Philips Semiconductors
56 FX-bus
63 ---------------------------------------
64 This control is used to attenuate samples for left and right PCM FX-bus
66 The result samples are forwarded to the front DAC PCM slots of the AC97 codec.
69 ------------------------------------------------
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/Documentation/devicetree/bindings/display/bridge/
Dsii902x.txt4 - compatible: "sil,sii9022"
5 - reg: i2c address of the bridge
8 - interrupts: describe the interrupt line used to inform the host
10 - reset-gpios: OF device-tree gpio specification for RST_N pin.
11 - iovcc-supply: I/O Supply Voltage (1.8V or 3.3V)
12 - cvcc12-supply: Digital Core Supply Voltage (1.2V)
15 - #sound-dai-cells: <0> or <1>. <0> if only i2s or spdif pin
18 - sil,i2s-data-lanes: Array of up to 4 integers with values of 0-3
23 pins (SD0 - SD3). Any i2s pin can be connected to any fifo,
28 - clocks: phandle and clock specifier for each clock listed in
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